diff --git a/controller.sv b/controller.sv
index 70c627c3..cbe313bc 100644
--- a/controller.sv
+++ b/controller.sv
@@ -229,14 +229,25 @@ module riscv_controller
           ctrl_fsm_ns = DECODE;
         end
 
-        // TODO: Check if we need to handle IRQs here
-
         // hwloop detected, jump to start address!
         // Attention: This has to be done in the DECODE and the FIRST_FETCH states
         if (hwloop_jump_i == 1'b1) begin
-          pc_mux_sel_o  = `PC_HWLOOP;
+          pc_mux_sel_o = `PC_HWLOOP;
           pc_set_o     = 1'b1;
         end
+
+        // handle exceptions
+        if (exc_req_i) begin
+          pc_mux_sel_o = `PC_EXCEPTION;
+          pc_set_o     = 1'b1;
+          exc_ack_o    = 1'b1;
+
+          // TODO: Check
+          if (jump_in_dec_i == `BRANCH_JALR || jump_in_dec_i == `BRANCH_JAL)
+            save_pc_if_o = 1'b1;
+          else
+            save_pc_id_o = 1'b1;
+        end
       end
 
       DECODE:
diff --git a/exc_controller.sv b/exc_controller.sv
index 6df2a07c..aaa7ea94 100644
--- a/exc_controller.sv
+++ b/exc_controller.sv
@@ -81,9 +81,10 @@ module riscv_exc_controller
       pc_mux_int = `EXC_PC_ECALL;
     end
 
-    if (illegal_insn_i)
+    if (illegal_insn_i) begin
       cause_int  = 6'b0_00010;
       pc_mux_int = `EXC_PC_ILLINSN;
+    end
   end
 
   always_ff @(posedge clk, negedge rst_n)
@@ -116,10 +117,12 @@ module riscv_exc_controller
     unique case (exc_ctrl_cs)
       IDLE:
       begin
-        req_o = req_int;
+        if (irq_enable_i) begin
+          req_o = req_int;
 
-        if (req_int)
-          exc_ctrl_ns = WAIT_CONTROLLER;
+          if (req_int)
+            exc_ctrl_ns = WAIT_CONTROLLER;
+        end
       end
 
       WAIT_CONTROLLER: