diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile
index f31ee49a..25cca613 100644
--- a/dv/uvm/core_ibex/Makefile
+++ b/dv/uvm/core_ibex/Makefile
@@ -51,14 +51,8 @@ ISS                 := spike
 # ISS runtime options
 ISS_OPTS            :=
 # ISA
-# Both an updated compiler and ISS are required to verify the bitmanip v.1.00
-# and draft v.0.93 extensions. For now, disable the bitmanip tests and verify
-# RV32IMC only.
-# For details, refer to https://github.com/lowRISC/ibex/issues/1470
-#ISA                 := rv32imcb
-#ISA_ISS             := rv32imc_Zba_Zbb_Zbc_Zbs_Xbitmanip
-ISA                 := rv32imc
-ISA_ISS             := rv32imc
+ISA                 := rv32imcb
+ISA_ISS             := rv32imc_Zba_Zbb_Zbc_Zbs_Xbitmanip
 # Test name (default: full regression)
 TEST                := all
 TESTLIST            := riscv_dv_extension/testlist.yaml
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index 13d6d4b6..fb422ed0 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -719,52 +719,52 @@
 # Both an updated compiler and ISS are required to verify the bitmanip v.1.00
 # and draft v.0.93 extensions. For now, disable the bitmanip tests.
 # For details, refer to https://github.com/lowRISC/ibex/issues/1470
-#- test: riscv_bitmanip_full_test
-#  desc: >
-#    Random instruction test with supported B extension instructions in full configuration
-#  iterations: 10
-#  gen_test: riscv_rand_instr_test
-#  gen_opts: >
-#    +enable_zba_extension=1
-#    +enable_zbb_extension=1
-#    +enable_zbc_extension=1
-#    +enable_zbs_extension=1
-#    +enable_b_extension=1
-#    +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
-#    +disable_cosim=1
-#  rtl_test: core_ibex_base_test
-#  rtl_params:
-#    RV32B: "ibex_pkg::RV32BFull"
-#
-#- test: riscv_bitmanip_otearlgrey_test
-#  desc: >
-#    Random instruction test with supported B extension instructions in OTEarlGrey configuration
-#  iterations: 10
-#  gen_test: riscv_rand_instr_test
-#  gen_opts: >
-#    +enable_zba_extension=1
-#    +enable_zbb_extension=1
-#    +enable_zbc_extension=1
-#    +enable_zbs_extension=1
-#    +enable_b_extension=1
-#    +enable_bitmanip_groups=zbf,zbp,zbr,zbt
-#    +disable_cosim=1
-#  rtl_test: core_ibex_base_test
-#  rtl_params:
-#    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey"]
-#
-#- test: riscv_bitmanip_balanced_test
-#  desc: >
-#    Random instruction test with supported B extension instructions in balanced configuration
-#  iterations: 10
-#  gen_test: riscv_rand_instr_test
-#  gen_opts: >
-#    +enable_zba_extension=1
-#    +enable_zbb_extension=1
-#    +enable_zbs_extension=1
-#    +enable_b_extension=1
-#    +enable_bitmanip_groups=zbf,zbt
-#    +disable_cosim=1
-#  rtl_test: core_ibex_base_test
-#  rtl_params:
-#    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey", "ibex_pkg::RV32BBalanced"]
+- test: riscv_bitmanip_full_test
+  desc: >
+    Random instruction test with supported B extension instructions in full configuration
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbc_extension=1
+    +enable_zbs_extension=1
+    +enable_b_extension=1
+    +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
+    +disable_cosim=1
+  rtl_test: core_ibex_base_test
+  rtl_params:
+    RV32B: "ibex_pkg::RV32BFull"
+
+- test: riscv_bitmanip_otearlgrey_test
+  desc: >
+    Random instruction test with supported B extension instructions in OTEarlGrey configuration
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbc_extension=1
+    +enable_zbs_extension=1
+    +enable_b_extension=1
+    +enable_bitmanip_groups=zbf,zbp,zbr,zbt
+    +disable_cosim=1
+  rtl_test: core_ibex_base_test
+  rtl_params:
+    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey"]
+
+- test: riscv_bitmanip_balanced_test
+  desc: >
+    Random instruction test with supported B extension instructions in balanced configuration
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbs_extension=1
+    +enable_b_extension=1
+    +enable_bitmanip_groups=zbf,zbt
+    +disable_cosim=1
+  rtl_test: core_ibex_base_test
+  rtl_params:
+    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey", "ibex_pkg::RV32BBalanced"]