diff --git a/doc/03_reference/icache.rst b/doc/03_reference/icache.rst
index 75115ebb..bfabb58c 100644
--- a/doc/03_reference/icache.rst
+++ b/doc/03_reference/icache.rst
@@ -96,7 +96,7 @@ Indicative RAM sizes for common configurations are given in the table below:
 If ICacheScramble parameter is enabled, all RAM primitives are replaced with scrambling RAM primitive.
 For more information about how scrambling works internally (see :file:`vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md`).
 Interface for receiving scrambling key follows req / ack protocol.
-Ibex first requests a new ephemeral key by asserting the request (``scramble_req_o``) and when a fresh valid key is indicated by ``scramble_key_valid_i``, it deasserts the request. 
+Ibex first requests a new ephemeral key by asserting the request (``scramble_req_o``) and when a fresh valid key is indicated by ``scramble_key_valid_i``, it deasserts the request.
 Note that in current implementation, it is assumed req/ack protocol is synchronized before arriving to Ibex top level.
 
 Sub Unit Description
diff --git a/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv b/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv
index fe0b01e1..f9782b80 100644
--- a/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv
+++ b/dv/uvm/icache/dv/env/ibex_icache_scoreboard.sv
@@ -427,7 +427,7 @@ class ibex_icache_scoreboard
     bit [BusWidth-1:0] rdata;
 
     bit [31:0]         seed;
-    int unsigned       mem_err_shift;      
+    int unsigned       mem_err_shift;
 
     bus_shift = $clog2(BusWidth / 8);
     addr_lo = (address >> bus_shift) << bus_shift;
diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
index 4493a8ae..b30fed1c 100644
--- a/examples/fpga/artya7/top_artya7.core
+++ b/examples/fpga/artya7/top_artya7.core
@@ -41,7 +41,7 @@ parameters:
     datatype: str
     paramtype: vlogdefine
     description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
- 
+
   FPGAPowerAnalysis:
     datatype: int
     paramtype: vlogparam