From 394a0d21603494b55de38f1f52ed0ffe7032867a Mon Sep 17 00:00:00 2001 From: Canberk Topal Date: Wed, 27 Apr 2022 15:59:39 +0100 Subject: [PATCH] Updating parameters for OpenTitan option Updated the parameters with respect to top_earlgrey.hjson in OpenTitan repository. For other builds, kept the previously undeclared parameters as their default values. Signed-off-by: Canberk Topal --- .../ibex_riscv_compliance.core | 35 ++++++++-- .../rtl/ibex_riscv_compliance.sv | 66 ++++++++++-------- dv/uvm/core_ibex/tb/core_ibex_tb_top.sv | 68 +++++++++++-------- .../ibex_simple_system_cosim.core | 21 ++++++ .../simple_system/ibex_simple_system.core | 21 ++++++ .../simple_system/rtl/ibex_simple_system.sv | 39 ++++++----- ibex_configs.yaml | 56 ++++++++++----- ibex_core.core | 24 +++++++ ibex_top.core | 18 +++++ ibex_top_tracing.core | 21 ++++++ util/ibex_config.py | 14 ++-- 11 files changed, 279 insertions(+), 104 deletions(-) diff --git a/dv/riscv_compliance/ibex_riscv_compliance.core b/dv/riscv_compliance/ibex_riscv_compliance.core index 919b483b..6f53ee3f 100644 --- a/dv/riscv_compliance/ibex_riscv_compliance.core +++ b/dv/riscv_compliance/ibex_riscv_compliance.core @@ -77,6 +77,24 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + + SecureIbex: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enables security hardening features (EXPERIMENTAL) [0/1]" + + ICacheScramble: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" + PMPEnable: datatype: int default: 0 @@ -95,17 +113,17 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" - SecureIbex: + MHPMCounterNum: datatype: int paramtype: vlogparam default: 0 - description: "Enables security hardening features (EXPERIMENTAL) [0/1]" + description: Number of performance monitor event counters [0/29] - ICacheScramble: + MHPMCounterWidth: datatype: int paramtype: vlogparam - default: 0 - description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" + default: 40 + description: Bit width of performance monitor event counters [32/64] targets: sim: @@ -123,11 +141,14 @@ targets: - BranchTargetALU - WritebackStage - BranchPredictor + - DbgTriggerEn + - SecureIbex + - ICacheScramble - PMPEnable - PMPGranularity - PMPNumRegions - - SecureIbex - - ICacheScramble + - MHPMCounterNum + - MHPMCounterWidth toplevel: ibex_riscv_compliance tools: verilator: diff --git a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv index 27268ade..dd1c0942 100644 --- a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv +++ b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv @@ -15,20 +15,23 @@ module ibex_riscv_compliance ( input IO_RST_N ); - parameter bit PMPEnable = 1'b0; - parameter int unsigned PMPGranularity = 0; - parameter int unsigned PMPNumRegions = 4; - parameter bit RV32E = 1'b0; - parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast; - parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone; - parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF; - parameter bit BranchTargetALU = 1'b0; - parameter bit WritebackStage = 1'b0; - parameter bit ICache = 1'b0; - parameter bit ICacheECC = 1'b0; - parameter bit BranchPredictor = 1'b0; - parameter bit SecureIbex = 1'b0; - parameter bit ICacheScramble = 1'b0; + parameter bit PMPEnable = 1'b0; + parameter int unsigned PMPGranularity = 0; + parameter int unsigned PMPNumRegions = 4; + parameter int unsigned MHPMCounterNum = 0; + parameter int unsigned MHPMCounterWidth = 40; + parameter bit RV32E = 1'b0; + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast; + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone; + parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF; + parameter bit BranchTargetALU = 1'b0; + parameter bit WritebackStage = 1'b0; + parameter bit ICache = 1'b0; + parameter bit ICacheECC = 1'b0; + parameter bit BranchPredictor = 1'b0; + parameter bit SecureIbex = 1'b0; + parameter bit ICacheScramble = 1'b0; + parameter bit DbgTriggerEn = 1'b0; logic clk_sys, rst_sys_n; @@ -135,22 +138,25 @@ module ibex_riscv_compliance ( end ibex_top_tracing #( - .PMPEnable (PMPEnable ), - .PMPGranularity (PMPGranularity ), - .PMPNumRegions (PMPNumRegions ), - .RV32E (RV32E ), - .RV32M (RV32M ), - .RV32B (RV32B ), - .RegFile (RegFile ), - .BranchTargetALU (BranchTargetALU ), - .WritebackStage (WritebackStage ), - .ICache (ICache ), - .ICacheECC (ICacheECC ), - .BranchPredictor (BranchPredictor ), - .SecureIbex (SecureIbex ), - .ICacheScramble (ICacheScramble ), - .DmHaltAddr (32'h00000000 ), - .DmExceptionAddr (32'h00000000 ) + .PMPEnable (PMPEnable ), + .PMPGranularity (PMPGranularity ), + .PMPNumRegions (PMPNumRegions ), + .MHPMCounterNum (MHPMCounterNum ), + .MHPMCounterWidth (MHPMCounterWidth ), + .RV32E (RV32E ), + .RV32M (RV32M ), + .RV32B (RV32B ), + .RegFile (RegFile ), + .BranchTargetALU (BranchTargetALU ), + .WritebackStage (WritebackStage ), + .ICache (ICache ), + .ICacheECC (ICacheECC ), + .BranchPredictor (BranchPredictor ), + .DbgTriggerEn (DbgTriggerEn ), + .SecureIbex (SecureIbex ), + .ICacheScramble (ICacheScramble ), + .DmHaltAddr (32'h00000000 ), + .DmExceptionAddr (32'h00000000 ) ) u_top ( .clk_i (clk_sys ), .rst_ni (rst_sys_n ), diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv index 3d2898c0..0efc4a5f 100644 --- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv +++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv @@ -51,38 +51,46 @@ module core_ibex_tb_top; `define IBEX_CFG_RegFile ibex_pkg::RegFileFF `endif - parameter bit PMPEnable = 1'b0; - parameter int unsigned PMPGranularity = 0; - parameter int unsigned PMPNumRegions = 4; - parameter bit RV32E = 1'b0; - parameter ibex_pkg::rv32m_e RV32M = `IBEX_CFG_RV32M; - parameter ibex_pkg::rv32b_e RV32B = `IBEX_CFG_RV32B; - parameter ibex_pkg::regfile_e RegFile = `IBEX_CFG_RegFile; - parameter bit BranchTargetALU = 1'b0; - parameter bit WritebackStage = 1'b0; - parameter bit ICache = 1'b0; - parameter bit ICacheECC = 1'b0; - parameter bit BranchPredictor = 1'b0; - parameter bit SecureIbex = 1'b0; - parameter bit ICacheScramble = 1'b0; + parameter bit PMPEnable = 1'b0; + parameter int unsigned PMPGranularity = 0; + parameter int unsigned PMPNumRegions = 4; + parameter int unsigned MHPMCounterNum = 0; + parameter int unsigned MHPMCounterWidth = 40; + parameter bit RV32E = 1'b0; + parameter ibex_pkg::rv32m_e RV32M = `IBEX_CFG_RV32M; + parameter ibex_pkg::rv32b_e RV32B = `IBEX_CFG_RV32B; + parameter ibex_pkg::regfile_e RegFile = `IBEX_CFG_RegFile; + parameter bit BranchTargetALU = 1'b0; + parameter bit WritebackStage = 1'b0; + parameter bit ICache = 1'b0; + parameter bit ICacheECC = 1'b0; + parameter bit BranchPredictor = 1'b0; + parameter bit SecureIbex = 1'b0; + parameter bit ICacheScramble = 1'b0; + parameter bit DbgTriggerEn = 1'b0; + ibex_top_tracing #( - .DmHaltAddr (32'h`BOOT_ADDR + 'h0 ), - .DmExceptionAddr (32'h`BOOT_ADDR + 'h4 ), - .PMPEnable (PMPEnable ), - .PMPGranularity (PMPGranularity ), - .PMPNumRegions (PMPNumRegions ), - .RV32E (RV32E ), - .RV32M (RV32M ), - .RV32B (RV32B ), - .RegFile (RegFile ), - .BranchTargetALU (BranchTargetALU ), - .WritebackStage (WritebackStage ), - .ICache (ICache ), - .ICacheECC (ICacheECC ), - .SecureIbex (SecureIbex ), - .ICacheScramble (ICacheScramble ), - .BranchPredictor (BranchPredictor ) + .DmHaltAddr (32'h`BOOT_ADDR + 'h0 ), + .DmExceptionAddr (32'h`BOOT_ADDR + 'h4 ), + .PMPEnable (PMPEnable ), + .PMPGranularity (PMPGranularity ), + .PMPNumRegions (PMPNumRegions ), + .MHPMCounterNum (MHPMCounterNum ), + .MHPMCounterWidth (MHPMCounterWidth ), + .RV32E (RV32E ), + .RV32M (RV32M ), + .RV32B (RV32B ), + .RegFile (RegFile ), + .BranchTargetALU (BranchTargetALU ), + .WritebackStage (WritebackStage ), + .ICache (ICache ), + .ICacheECC (ICacheECC ), + .SecureIbex (SecureIbex ), + .ICacheScramble (ICacheScramble ), + .BranchPredictor (BranchPredictor ), + .DbgTriggerEn (DbgTriggerEn ) + ) dut ( .clk_i (clk ), .rst_ni (rst_n ), diff --git a/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core b/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core index 12df17c1..958540e7 100644 --- a/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core +++ b/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core @@ -82,6 +82,12 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + PMPEnable: datatype: int default: 0 @@ -100,6 +106,18 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" + MHPMCounterNum: + datatype: int + paramtype: vlogparam + default: 0 + description: Number of performance monitor event counters [0/29] + + MHPMCounterWidth: + datatype: int + paramtype: vlogparam + default: 40 + description: Bit width of performance monitor event counters [32/64] + ICacheScramble: datatype: int default: 0 @@ -122,9 +140,12 @@ targets: - WritebackStage - SecureIbex - BranchPredictor + - DbgTriggerEn - PMPEnable - PMPGranularity - PMPNumRegions + - MHPMCounterNum + - MHPMCounterWidth - ICacheScramble - SRAMInitFile diff --git a/examples/simple_system/ibex_simple_system.core b/examples/simple_system/ibex_simple_system.core index 3bcaaf69..0e3e723f 100644 --- a/examples/simple_system/ibex_simple_system.core +++ b/examples/simple_system/ibex_simple_system.core @@ -84,6 +84,12 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + PMPEnable: datatype: int default: 0 @@ -102,6 +108,18 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" + MHPMCounterNum: + datatype: int + paramtype: vlogparam + default: 0 + description: Number of performance monitor event counters [0/29] + + MHPMCounterWidth: + datatype: int + paramtype: vlogparam + default: 40 + description: Bit width of performance monitor event counters [32/64] + targets: default: &default_target filesets: @@ -119,9 +137,12 @@ targets: - WritebackStage - SecureIbex - BranchPredictor + - DbgTriggerEn - PMPEnable - PMPGranularity - PMPNumRegions + - MHPMCounterNum + - MHPMCounterWidth - SRAMInitFile lint: diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv index 275f9259..42111447 100644 --- a/examples/simple_system/rtl/ibex_simple_system.sv +++ b/examples/simple_system/rtl/ibex_simple_system.sv @@ -40,6 +40,8 @@ module ibex_simple_system ( parameter bit PMPEnable = 1'b0; parameter int unsigned PMPGranularity = 0; parameter int unsigned PMPNumRegions = 4; + parameter int unsigned MHPMCounterNum = 0; + parameter int unsigned MHPMCounterWidth = 40; parameter bit RV32E = 1'b0; parameter ibex_pkg::rv32m_e RV32M = `RV32M; parameter ibex_pkg::rv32b_e RV32B = `RV32B; @@ -47,6 +49,7 @@ module ibex_simple_system ( parameter bit BranchTargetALU = 1'b0; parameter bit WritebackStage = 1'b0; parameter bit ICache = 1'b0; + parameter bit DbgTriggerEn = 1'b0; parameter bit ICacheECC = 1'b0; parameter bit BranchPredictor = 1'b0; parameter SRAMInitFile = ""; @@ -184,23 +187,25 @@ module ibex_simple_system ( end ibex_top_tracing #( - .SecureIbex ( SecureIbex ), - .ICacheScramble ( ICacheScramble ), - .PMPEnable ( PMPEnable ), - .PMPGranularity ( PMPGranularity ), - .PMPNumRegions ( PMPNumRegions ), - .MHPMCounterNum ( 29 ), - .RV32E ( RV32E ), - .RV32M ( RV32M ), - .RV32B ( RV32B ), - .RegFile ( RegFile ), - .BranchTargetALU ( BranchTargetALU ), - .ICache ( ICache ), - .ICacheECC ( ICacheECC ), - .WritebackStage ( WritebackStage ), - .BranchPredictor ( BranchPredictor ), - .DmHaltAddr ( 32'h00100000 ), - .DmExceptionAddr ( 32'h00100000 ) + .SecureIbex ( SecureIbex ), + .ICacheScramble ( ICacheScramble ), + .PMPEnable ( PMPEnable ), + .PMPGranularity ( PMPGranularity ), + .PMPNumRegions ( PMPNumRegions ), + .MHPMCounterNum ( 29 ), + .MHPMCounterWidth( MHPMCounterWidth ), + .RV32E ( RV32E ), + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .RegFile ( RegFile ), + .BranchTargetALU ( BranchTargetALU ), + .ICache ( ICache ), + .ICacheECC ( ICacheECC ), + .WritebackStage ( WritebackStage ), + .BranchPredictor ( BranchPredictor ), + .DbgTriggerEn ( DbgTriggerEn ), + .DmHaltAddr ( 32'h00100000 ), + .DmExceptionAddr ( 32'h00100000 ) ) u_top ( .clk_i (clk_sys), .rst_ni (rst_sys_n), diff --git a/ibex_configs.yaml b/ibex_configs.yaml index ccaa01d2..4b693d0e 100644 --- a/ibex_configs.yaml +++ b/ibex_configs.yaml @@ -16,12 +16,15 @@ small: WritebackStage : 0 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 0 PMPGranularity : 0 PMPNumRegions : 4 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # Configuration to match that used in the OpenTitan project opentitan: @@ -33,12 +36,15 @@ opentitan: WritebackStage : 1 ICache : 1 ICacheECC : 1 + ICacheScramble : 1 BranchPredictor : 0 + DbgTriggerEn : 1 + SecureIbex : 1 PMPEnable : 1 PMPGranularity : 0 PMPNumRegions : 16 - SecureIbex : 1 - ICacheScramble : 0 + MHPMCounterNum : 10 + MHPMCounterWidth : 32 # =============================== # * EXPERIMENTAL CONFIGURATIONS * @@ -56,12 +62,15 @@ experimental-maxperf: WritebackStage : 1 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 0 PMPGranularity : 0 PMPNumRegions : 4 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # experimental-maxperf config above plus PMP enabled with 16 regions. experimental-maxperf-pmp: @@ -73,12 +82,15 @@ experimental-maxperf-pmp: WritebackStage : 1 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 1 PMPGranularity : 0 PMPNumRegions : 16 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # experimental-maxperf-pmp config above with balanced bitmanip extension experimental-maxperf-pmp-bmbalanced: @@ -90,12 +102,15 @@ experimental-maxperf-pmp-bmbalanced: WritebackStage : 1 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 1 PMPGranularity : 0 PMPNumRegions : 16 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # experimental-maxperf-pmp config above with full bitmanip extension experimental-maxperf-pmp-bmfull: @@ -107,12 +122,15 @@ experimental-maxperf-pmp-bmfull: WritebackStage : 1 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 1 PMPGranularity : 0 PMPNumRegions : 16 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # experimental-maxperf-pmp-bmfull config above with icache enabled experimental-maxperf-pmp-bmfull-icache: @@ -124,12 +142,15 @@ experimental-maxperf-pmp-bmfull-icache: WritebackStage : 1 ICache : 1 ICacheECC : 1 + ICacheScramble : 0 BranchPredictor : 0 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 1 PMPGranularity : 0 PMPNumRegions : 16 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 # experimental-maxperf with branch predictor switched on. This exists to allow # easy use of Ibex with the branch predictor in particular for CI runs. The @@ -144,10 +165,13 @@ experimental-branch-predictor: WritebackStage : 1 ICache : 0 ICacheECC : 0 + ICacheScramble : 0 BranchPredictor : 1 + DbgTriggerEn : 0 + SecureIbex : 0 PMPEnable : 0 PMPGranularity : 0 PMPNumRegions : 4 - SecureIbex : 0 - ICacheScramble : 0 + MHPMCounterNum : 0 + MHPMCounterWidth : 40 diff --git a/ibex_core.core b/ibex_core.core index caf06034..c228c186 100644 --- a/ibex_core.core +++ b/ibex_core.core @@ -118,12 +118,24 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + SecureIbex: datatype: int default: 0 paramtype: vlogparam description: "Enables security hardening features (EXPERIMENTAL) [0/1]" + ICacheScramble: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]" + PMPEnable: datatype: int default: 0 @@ -142,6 +154,18 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" + MHPMCounterNum: + datatype: int + paramtype: vlogparam + default: 0 + description: Number of performance monitor event counters [0/29] + + MHPMCounterWidth: + datatype: int + paramtype: vlogparam + default: 40 + description: Bit width of performance monitor event counters [32/64] + targets: default: &default_target filesets: diff --git a/ibex_top.core b/ibex_top.core index 706ee9a5..20553b31 100644 --- a/ibex_top.core +++ b/ibex_top.core @@ -103,6 +103,12 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + SecureIbex: datatype: int default: 0 @@ -133,6 +139,18 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" + MHPMCounterNum: + datatype: int + paramtype: vlogparam + default: 0 + description: Number of performance monitor event counters [0/29] + + MHPMCounterWidth: + datatype: int + paramtype: vlogparam + default: 40 + description: Bit width of performance monitor event counters [32/64] + targets: default: &default_target filesets: diff --git a/ibex_top_tracing.core b/ibex_top_tracing.core index ef4dab5d..f52c5c00 100644 --- a/ibex_top_tracing.core +++ b/ibex_top_tracing.core @@ -77,6 +77,12 @@ parameters: default: 0 description: "Enables static branch prediction (EXPERIMENTAL)" + DbgTriggerEn: + datatype: int + default: 0 + paramtype: vlogparam + description: "Enable support for debug triggers. " + SecureIbex: datatype: int default: 0 @@ -107,6 +113,18 @@ parameters: paramtype: vlogparam description: "Number of PMP regions" + MHPMCounterNum: + datatype: int + paramtype: vlogparam + default: 0 + description: Number of performance monitor event counters [0/29] + + MHPMCounterWidth: + datatype: int + paramtype: vlogparam + default: 40 + description: Bit width of performance monitor event counters [32/64] + targets: default: &default_target filesets: @@ -129,11 +147,14 @@ targets: - BranchTargetALU - WritebackStage - BranchPredictor + - DbgTriggerEn - SecureIbex - ICacheScramble - PMPEnable - PMPGranularity - PMPNumRegions + - MHPMCounterNum + - MHPMCounterWidth default_tool: verilator tools: verilator: diff --git a/util/ibex_config.py b/util/ibex_config.py index 3b5b2c8e..3396f7e7 100755 --- a/util/ibex_config.py +++ b/util/ibex_config.py @@ -29,12 +29,15 @@ class Config: ('WritebackStage', bool), ('ICache', bool), ('ICacheECC', bool), + ('ICacheScramble', bool), ('BranchPredictor', bool), + ('DbgTriggerEn', bool), + ('SecureIbex', bool), ('PMPEnable', bool), ('PMPGranularity', int), ('PMPNumRegions', int), - ('SecureIbex', bool), - ('ICacheScramble', bool) + ('MHPMCounterNum', int), + ('MHPMCounterWidth', int) ] def __init__(self, yml): @@ -64,12 +67,15 @@ class Config: self.writeback_stage = Config.read_bool('WritebackStage', yml) self.icache = Config.read_bool('ICache', yml) self.icache_ecc = Config.read_bool('ICacheECC', yml) + self.icache_scramble = Config.read_bool('ICacheScramble', yml) self.branch_predictor = Config.read_bool('BranchPredictor', yml) + self.dbg_trigger_en = Config.read_bool('DbgTriggerEn', yml) + self.secure_ibex = Config.read_bool('SecureIbex', yml) self.pmp_enable = Config.read_bool('PMPEnable', yml) self.pmp_granularity = Config.read_int('PMPGranularity', yml) self.pmp_num_regions = Config.read_int('PMPNumRegions', yml) - self.secure_ibex = Config.read_bool('SecureIbex', yml) - self.icache_scramble = Config.read_bool('ICacheScramble', yml) + self.mhpm_counter_num = Config.read_int('MHPMCounterNum', yml) + self.mhpm_counter_width = Config.read_int('MHPMCounterWidth', yml) @staticmethod def read_bool(fld, yml):