diff --git a/cs_registers.sv b/cs_registers.sv
index 2ef2da06..1c355c86 100644
--- a/cs_registers.sv
+++ b/cs_registers.sv
@@ -47,7 +47,6 @@ module cs_registers
   input logic         save_pc_if_i,
   input logic         save_pc_id_i, // TODO: check if both IF/ID pc save is needed
   output logic [31:0] epcr_o,
-  output logic        irq_enable_o, // TODO: check if needed
 
   // HWLoop Signals
   input  logic [`HWLOOP_REGS-1:0] [31:0] hwlp_start_addr_i,
@@ -102,11 +101,6 @@ module cs_registers
       12'hF01: constant_rdata_int = 32'h00_00_80_00;  // mimpid: PULP3, anonymous source (no allocated ID)
       12'hF10: constant_rdata_int = {22'b0, cluster_id_i, core_id_i}; // mhartid: unique hardware thread id
 
-      // debug registers
-      12'hFC0: constant_rdata_int = curr_pc_id_i; // Previous Program Counter for Debug
-
-      12'h780: constant_rdata_int = curr_pc_if_i; // Next Program Counter for Debug
-
       default: is_constant = 1'b0;
     endcase
   end
diff --git a/debug_unit.sv b/debug_unit.sv
index ab832afd..9cb6fcaf 100644
--- a/debug_unit.sv
+++ b/debug_unit.sv
@@ -61,7 +61,10 @@ module debug_unit
   output logic [31:0]  regfile_wdata_o,
   input  logic [31:0]  regfile_rdata_i,
 
-  // Signals for NPC register
+  // Signals for PPC & NPC register
+  input logic  [31:0] curr_pc_if_i,
+  input logic  [31:0] curr_pc_id_i,
+
   output logic [31:0] npc_o,
   output logic        set_npc_o
 
@@ -131,8 +134,6 @@ module debug_unit
   assign dbg_st_en_o       = DMR1_DP[0];
   assign dbg_dsr_o         = DSR_DP;
 
-  // handle set next program counter
-  assign set_npc_o = (regfile_addr_o == 12'h780) && (sp_mux_o == 1'b1) && (regfile_we_o == 1'b1);
   assign npc_o     = dbginf_data_i;
 
 
@@ -146,12 +147,23 @@ module debug_unit
     regfile_addr_o     = 'h0;
     regfile_mux_o      = 1'b0;
     sp_mux_o           = 1'b0;
+    set_npc_o          = 1'b0;
 
     if(dbginf_strobe_i == 1'b1) begin
       // address decoding, first stage: evaluate higher 5 Bits to detect if debug regs are accessed
       if(dbginf_addr_i[15:11] == 5'b00110) begin
         // second stage: evaluate Bits 10:0 to detect which part of debug registers is accessed
         casex(dbginf_addr_i[10:0])
+          11'd0: begin // NPC
+            set_npc_o = dbginf_we_i;
+
+            dbginf_data_o = curr_pc_if_i;
+          end
+
+          11'd1: begin // PPC
+            dbginf_data_o = curr_pc_id_i;
+          end
+
           11'd16: begin // SP_DMR1
             if(dbginf_we_i == 1'b1)
               DMR1_DN = dbginf_data_i[`DMR1_ST+1:`DMR1_ST];
diff --git a/riscv_core.sv b/riscv_core.sv
index b30bc7b0..b43be4f4 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -639,8 +639,7 @@ module riscv_core
       .curr_pc_id_i            ( current_pc_id         ), // from IF stage
       .save_pc_if_i            ( save_pc_if            ),
       .save_pc_id_i            ( save_pc_id            ),
-      .epcr_o                  ( epcr                  ),
-      .irq_enable_o            ( irq_enable            )
+      .epcr_o                  ( epcr                  )
     );
 
     // Mux for SPR access through Debug Unit
@@ -780,6 +779,9 @@ module riscv_core
       .regfile_wdata_o ( dbg_reg_wdata   ),
       .regfile_rdata_i ( dbg_rdata       ),
 
+      // signals for PPC and NPC
+      .curr_pc_if_i    ( current_pc_if   ), // from IF stage
+      .curr_pc_id_i    ( current_pc_id   ), // from IF stage
       .npc_o           ( dbg_npc         ), // PC from debug unit
       .set_npc_o       ( dbg_set_npc     )  // set PC to new value
     );