diff --git a/README.md b/README.md index 4ef29f7e..baeb6c22 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ -# zero-riscy: RISC-V Core +# ibex: RISC-V Core -*zero-riscy** is a small 2-stage RISC-V core derived from RI5CY. +**ibex** is a small 2-stage RISC-V core derived from RI5CY. -**zero-riscy** fully implements the RV32IMC instruction set and a minimal +**ibex** fully implements the RV32IMC instruction set and a minimal set of RISCV privileged specifications. -**zero-riscy** can be configured to be very small by disabling the RV32M extensions +**ibex** can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions. This configuration is called **micro-riscy** The core was developed as part of the [PULP platform](http://pulp.ethz.ch/) for @@ -14,5 +14,5 @@ PULP and PULPino. ## Documentation A datasheet that explains the most important features of the core can be found -in the doc folder. +in the doc folder. diff --git a/zeroriscy_alu.sv b/ibex_alu.sv similarity index 98% rename from zeroriscy_alu.sv rename to ibex_alu.sv index 4ecf827c..f29c996e 100644 --- a/zeroriscy_alu.sv +++ b/ibex_alu.sv @@ -16,18 +16,18 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: ALU // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Arithmetic logic unit of the pipelined processor. // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_alu +module ibex_alu ( input logic [ALU_OP_WIDTH-1:0] operator_i, input logic [31:0] operand_a_i, diff --git a/zeroriscy_compressed_decoder.sv b/ibex_compressed_decoder.sv similarity index 98% rename from zeroriscy_compressed_decoder.sv rename to ibex_compressed_decoder.sv index 2303bb1c..860f2a19 100644 --- a/zeroriscy_compressed_decoder.sv +++ b/ibex_compressed_decoder.sv @@ -13,7 +13,7 @@ // Engineer: Sven Stucki - svstucki@student.ethz.ch // // // // Design Name: Compressed instruction decoder // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Decodes RISC-V compressed instructions into their RV32 // @@ -22,9 +22,9 @@ //////////////////////////////////////////////////////////////////////////////// -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_compressed_decoder +module ibex_compressed_decoder ( input logic [31:0] instr_i, output logic [31:0] instr_o, diff --git a/zeroriscy_controller.sv b/ibex_controller.sv similarity index 98% rename from zeroriscy_controller.sv rename to ibex_controller.sv index 2688a54c..ed02424a 100644 --- a/zeroriscy_controller.sv +++ b/ibex_controller.sv @@ -18,19 +18,19 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Main controller // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Main CPU controller of the processor // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_controller +module ibex_controller #( parameter REG_ADDR_WIDTH = 5 ) @@ -134,8 +134,8 @@ module zeroriscy_controller begin // print warning in case of decoding errors if (is_decoding_o && illegal_insn_i) begin - $display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, zeroriscy_core.core_id_i, - zeroriscy_id_stage.pc_id_i); + $display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, ibex_core.core_id_i, + ibex_id_stage.pc_id_i); end end // synopsys translate_on diff --git a/zeroriscy_core.sv b/ibex_core.sv similarity index 98% rename from zeroriscy_core.sv rename to ibex_core.sv index 82bcf4dd..581ee929 100644 --- a/zeroriscy_core.sv +++ b/ibex_core.sv @@ -19,18 +19,18 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Top level module // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Top level module of the RISC-V core. // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_core +module ibex_core #( parameter N_EXT_PERF_COUNTERS = 0, parameter RV32E = 0, @@ -266,7 +266,7 @@ module zeroriscy_core // main clock gate of the core // generates all clocks except the one for the debug unit which is // independent - cluster_clock_gating core_clock_gate_i + clock_gating core_clock_gate_i ( .clk_i ( clk_i ), .en_i ( clock_en ), @@ -282,7 +282,7 @@ module zeroriscy_core // |___|_| |____/ |_/_/ \_\____|_____| // // // ////////////////////////////////////////////////// - zeroriscy_if_stage if_stage_i + ibex_if_stage if_stage_i ( .clk ( clk ), .rst_n ( rst_ni ), @@ -341,7 +341,7 @@ module zeroriscy_core // |___|____/ |____/ |_/_/ \_\____|_____| // // // ///////////////////////////////////////////////// - zeroriscy_id_stage + ibex_id_stage #( .RV32E(RV32E), .RV32M(RV32M) @@ -459,7 +459,7 @@ module zeroriscy_core ); - zeroriscy_ex_block + ibex_ex_block #( //change the localparam MULT_TYPE to 0 or 1 //if you want a SLOW or FAST multiplier @@ -503,7 +503,7 @@ module zeroriscy_core // // //////////////////////////////////////////////////////////////////////////////////////// - zeroriscy_load_store_unit load_store_unit_i + ibex_load_store_unit load_store_unit_i ( .clk ( clk ), .rst_n ( rst_ni ), @@ -556,7 +556,7 @@ module zeroriscy_core // Control and Status Registers // ////////////////////////////////////// - zeroriscy_cs_registers + ibex_cs_registers #( .N_EXT_CNT ( N_EXT_PERF_COUNTERS ) ) @@ -627,7 +627,7 @@ module zeroriscy_core // // ///////////////////////////////////////////////////////////// - zeroriscy_debug_unit debug_unit_i + ibex_debug_unit debug_unit_i ( .clk ( clk_i ), // always-running clock for debug .rst_n ( rst_ni ), @@ -682,7 +682,7 @@ module zeroriscy_core `ifndef VERILATOR `ifdef TRACE_EXECUTION - zeroriscy_tracer zeroriscy_tracer_i + ibex_tracer ibex_tracer_i ( .clk ( clk_i ), // always-running clock for tracing .rst_n ( rst_ni ), diff --git a/zeroriscy_cs_registers.sv b/ibex_cs_registers.sv similarity index 98% rename from zeroriscy_cs_registers.sv rename to ibex_cs_registers.sv index a05645e0..5f128f09 100644 --- a/zeroriscy_cs_registers.sv +++ b/ibex_cs_registers.sv @@ -16,7 +16,7 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Control and Status Registers // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Control and Status Registers (CSRs) loosely following the // @@ -24,9 +24,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; `ifndef PULP_FPGA_EMUL `ifdef SYNTHESIS @@ -34,7 +34,7 @@ import zeroriscy_defines::*; `endif `endif -module zeroriscy_cs_registers +module ibex_cs_registers #( parameter N_EXT_CNT = 0 ) diff --git a/zeroriscy_debug_unit.sv b/ibex_debug_unit.sv similarity index 99% rename from zeroriscy_debug_unit.sv rename to ibex_debug_unit.sv index 0937e3f9..7a3209dd 100644 --- a/zeroriscy_debug_unit.sv +++ b/ibex_debug_unit.sv @@ -15,18 +15,18 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Debug Unit // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Debug controller // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_debug_unit +module ibex_debug_unit #( parameter REG_ADDR_WIDTH = 5 ) diff --git a/zeroriscy_decoder.sv b/ibex_decoder.sv similarity index 99% rename from zeroriscy_decoder.sv rename to ibex_decoder.sv index bc4253d9..7755f57a 100644 --- a/zeroriscy_decoder.sv +++ b/ibex_decoder.sv @@ -19,18 +19,18 @@ // Markus Wegmann - markus.wegmann@technokrat.ch // // // // Design Name: Decoder // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Decoder // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_decoder +module ibex_decoder #( parameter RV32M = 1 ) diff --git a/zeroriscy_ex_block.sv b/ibex_ex_block.sv similarity index 96% rename from zeroriscy_ex_block.sv rename to ibex_ex_block.sv index bb599b4a..dad03941 100644 --- a/zeroriscy_ex_block.sv +++ b/ibex_ex_block.sv @@ -19,18 +19,18 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Execute stage // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Execution block: Hosts ALU and MUL/DIV unit // // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_ex_block +module ibex_ex_block #( parameter RV32M = 1 ) @@ -106,7 +106,7 @@ endgenerate // // //////////////////////////// - zeroriscy_alu alu_i + ibex_alu alu_i ( .operator_i ( alu_operator_i ), .operand_a_i ( alu_operand_a_i ), @@ -132,7 +132,7 @@ endgenerate generate if (MULT_TYPE == 0) begin : multdiv_slow - zeroriscy_multdiv_slow multdiv_i + ibex_multdiv_slow multdiv_i ( .clk ( clk ), .rst_n ( rst_n ), @@ -151,7 +151,7 @@ endgenerate .multdiv_result_o ( multdiv_result ) ); end else begin: multdiv_fast - zeroriscy_multdiv_fast multdiv_i + ibex_multdiv_fast multdiv_i ( .clk ( clk ), .rst_n ( rst_n ), diff --git a/zeroriscy_fetch_fifo.sv b/ibex_fetch_fifo.sv similarity index 98% rename from zeroriscy_fetch_fifo.sv rename to ibex_fetch_fifo.sv index f47a0717..d6682e86 100644 --- a/zeroriscy_fetch_fifo.sv +++ b/ibex_fetch_fifo.sv @@ -12,18 +12,18 @@ // Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // // // // Design Name: Fetch Fifo for 32 bit memory interface // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Fetch fifo // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" // input port: send address one cycle before the data // clear_i clears the FIFO for the following cycle. in_addr_i can be sent in // this cycle already -module zeroriscy_fetch_fifo +module ibex_fetch_fifo ( input logic clk, input logic rst_n, diff --git a/zeroriscy_id_stage.sv b/ibex_id_stage.sv similarity index 99% rename from zeroriscy_id_stage.sv rename to ibex_id_stage.sv index c097d666..23bb8a40 100644 --- a/zeroriscy_id_stage.sv +++ b/ibex_id_stage.sv @@ -18,7 +18,7 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Instruction Decode Stage // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Decode stage of the core. It decodes the instructions // @@ -26,9 +26,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; // Source/Destination register instruction index @@ -37,7 +37,7 @@ import zeroriscy_defines::*; `define REG_D 11:07 -module zeroriscy_id_stage +module ibex_id_stage #( parameter RV32M = 1, parameter RV32E = 0 @@ -409,7 +409,7 @@ module zeroriscy_id_stage end end - zeroriscy_register_file + ibex_register_file #( .RV32E(RV32E) ) @@ -445,7 +445,7 @@ module zeroriscy_id_stage // // /////////////////////////////////////////////// - zeroriscy_decoder + ibex_decoder #( .RV32M(RV32M) ) @@ -508,7 +508,7 @@ module zeroriscy_id_stage // // //////////////////////////////////////////////////////////////////// - zeroriscy_controller controller_i + ibex_controller controller_i ( .clk ( clk ), .rst_n ( rst_n ), @@ -601,7 +601,7 @@ module zeroriscy_id_stage // // //////////////////////////////////////////////////////////////////////// - zeroriscy_int_controller int_controller_i + ibex_int_controller int_controller_i ( .clk ( clk ), .rst_n ( rst_n ), diff --git a/zeroriscy_if_stage.sv b/ibex_if_stage.sv similarity index 97% rename from zeroriscy_if_stage.sv rename to ibex_if_stage.sv index 079ccbd2..7a289fda 100644 --- a/zeroriscy_if_stage.sv +++ b/ibex_if_stage.sv @@ -17,7 +17,7 @@ // Sven Stucki - svstucki@student.ethz.ch // // // // Design Name: Instruction Fetch Stage // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Instruction fetch unit: Selection of the next PC, and // @@ -25,11 +25,11 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_if_stage +module ibex_if_stage ( input logic clk, input logic rst_n, @@ -121,7 +121,7 @@ module zeroriscy_if_stage end // prefetch buffer, caches a fixed number of instructions - zeroriscy_prefetch_buffer prefetch_buffer_i + ibex_prefetch_buffer prefetch_buffer_i ( .clk ( clk ), .rst_n ( rst_n ), @@ -224,7 +224,7 @@ module zeroriscy_if_stage logic illegal_c_insn; logic instr_compressed_int; - zeroriscy_compressed_decoder compressed_decoder_i + ibex_compressed_decoder compressed_decoder_i ( .instr_i ( fetch_rdata ), .instr_o ( instr_decompressed ), diff --git a/zeroriscy_int_controller.sv b/ibex_int_controller.sv similarity index 96% rename from zeroriscy_int_controller.sv rename to ibex_int_controller.sv index bb01cd5a..5d7fd395 100644 --- a/zeroriscy_int_controller.sv +++ b/ibex_int_controller.sv @@ -14,16 +14,16 @@ // Additional contributions by: // // // // Design Name: Interrupt Controller // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Interrupt Controller of the pipelined processor // // // //////////////////////////////////////////////////////////////////////////////// -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_int_controller +module ibex_int_controller ( input logic clk, input logic rst_n, diff --git a/zeroriscy_load_store_unit.sv b/ibex_load_store_unit.sv similarity index 99% rename from zeroriscy_load_store_unit.sv rename to ibex_load_store_unit.sv index 2efcfa1a..6d5845f5 100644 --- a/zeroriscy_load_store_unit.sv +++ b/ibex_load_store_unit.sv @@ -17,7 +17,7 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: Load Store Unit // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Load Store Unit, used to eliminate multiple access during // @@ -25,9 +25,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -module zeroriscy_load_store_unit +module ibex_load_store_unit ( input logic clk, input logic rst_n, diff --git a/zeroriscy_multdiv_fast.sv b/ibex_multdiv_fast.sv similarity index 98% rename from zeroriscy_multdiv_fast.sv rename to ibex_multdiv_fast.sv index 5b03e229..69aff6aa 100644 --- a/zeroriscy_multdiv_fast.sv +++ b/ibex_multdiv_fast.sv @@ -13,19 +13,19 @@ // // // // // Design Name: Fast Multiplier and Division // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: 16x16 kernel multiplier and Long Division // // // //////////////////////////////////////////////////////////////////////////////// -import zeroriscy_defines::*; +import ibex_defines::*; `define OP_L 15:0 `define OP_H 31:16 -module zeroriscy_multdiv_fast +module ibex_multdiv_fast ( input logic clk, input logic rst_n, @@ -336,4 +336,4 @@ module zeroriscy_multdiv_fast end -endmodule // zeroriscy_mult +endmodule // ibex_mult diff --git a/zeroriscy_multdiv_slow.sv b/ibex_multdiv_slow.sv similarity index 98% rename from zeroriscy_multdiv_slow.sv rename to ibex_multdiv_slow.sv index 1870e002..bd021006 100644 --- a/zeroriscy_multdiv_slow.sv +++ b/ibex_multdiv_slow.sv @@ -13,17 +13,17 @@ // // // // // Design Name: Slow Multiplier and Division // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Baugh-Wooley multiplier and Long Division // // // //////////////////////////////////////////////////////////////////////////////// -import zeroriscy_defines::*; +import ibex_defines::*; -module zeroriscy_multdiv_slow +module ibex_multdiv_slow ( input logic clk, input logic rst_n, @@ -297,4 +297,4 @@ module zeroriscy_multdiv_slow assign ready_o = (curr_state_q == MD_FINISH) | (curr_state_q == MD_LAST & (operator_i == MD_OP_MULL | operator_i == MD_OP_MULH)); -endmodule // zeroriscy_mult +endmodule // ibex_mult diff --git a/zeroriscy_prefetch_buffer.sv b/ibex_prefetch_buffer.sv similarity index 98% rename from zeroriscy_prefetch_buffer.sv rename to ibex_prefetch_buffer.sv index f43b210c..88b98d31 100644 --- a/zeroriscy_prefetch_buffer.sv +++ b/ibex_prefetch_buffer.sv @@ -12,7 +12,7 @@ // Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // // // // Design Name: Prefetcher Buffer for 32 bit memory interface // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Prefetch Buffer that caches instructions. This cuts overly // @@ -20,7 +20,7 @@ // // //////////////////////////////////////////////////////////////////////////////// -module zeroriscy_prefetch_buffer +module ibex_prefetch_buffer ( input logic clk, input logic rst_n, @@ -71,7 +71,7 @@ module zeroriscy_prefetch_buffer // consumes addresses and rdata ////////////////////////////////////////////////////////////////////////////// - zeroriscy_fetch_fifo fifo_i + ibex_fetch_fifo fifo_i ( .clk ( clk ), .rst_n ( rst_n ), diff --git a/zeroriscy_register_file.sv b/ibex_register_file.sv similarity index 96% rename from zeroriscy_register_file.sv rename to ibex_register_file.sv index 67fd421f..5da817f8 100644 --- a/zeroriscy_register_file.sv +++ b/ibex_register_file.sv @@ -16,7 +16,7 @@ // Markus Wegmann - markus.wegmann@technokrat.ch // // // // Design Name: RISC-V register file // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Register file with 31 or 15x 32 bit wide registers. // @@ -25,9 +25,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -module zeroriscy_register_file +module ibex_register_file #( parameter RV32E = 0, parameter DATA_WIDTH = 32 @@ -93,7 +93,7 @@ module zeroriscy_register_file // WRITE : SAMPLE INPUT DATA //--------------------------------------------------------------------------- - cluster_clock_gating CG_WE_GLOBAL + clock_gating CG_WE_GLOBAL ( .clk_i ( clk ), .en_i ( we_a_i ), @@ -133,7 +133,7 @@ module zeroriscy_register_file generate for(x = 1; x < NUM_WORDS; x++) begin : CG_CELL_WORD_ITER - cluster_clock_gating CG_Inst + clock_gating CG_Inst ( .clk_i ( clk_int ), .en_i ( waddr_onehot_a[x] ), diff --git a/zeroriscy_register_file_ff.sv b/ibex_register_file_ff.sv similarity index 96% rename from zeroriscy_register_file_ff.sv rename to ibex_register_file_ff.sv index 4572ef2f..2b448209 100644 --- a/zeroriscy_register_file_ff.sv +++ b/ibex_register_file_ff.sv @@ -15,7 +15,7 @@ // Markus Wegmann - markus.wegmann@technokrat.ch // // // // Design Name: RISC-V register file // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Register file with 31 or 15x 32 bit wide registers. // @@ -24,9 +24,9 @@ // // //////////////////////////////////////////////////////////////////////////////// -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -module zeroriscy_register_file +module ibex_register_file #( parameter RV32E = 0, parameter DATA_WIDTH = 32 diff --git a/zeroriscy_tracer.sv b/ibex_tracer.sv similarity index 98% rename from zeroriscy_tracer.sv rename to ibex_tracer.sv index b9594a4b..b1d5e543 100644 --- a/zeroriscy_tracer.sv +++ b/ibex_tracer.sv @@ -15,7 +15,7 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: RISC-V Tracer // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Traces the executed instructions // @@ -25,10 +25,10 @@ `ifndef VERILATOR -`include "zeroriscy_config.sv" +`include "ibex_config.sv" -import zeroriscy_defines::*; -import zeroriscy_tracer_defines::*; +import ibex_defines::*; +import ibex_tracer_defines::*; // Source/Destination register instruction index @@ -38,7 +38,7 @@ import zeroriscy_tracer_defines::*; `define REG_D 11:07 -module zeroriscy_tracer +module ibex_tracer #( parameter REG_ADDR_WIDTH = 5 ) @@ -441,4 +441,4 @@ module zeroriscy_tracer end // always @ (posedge clk) endmodule -`endif \ No newline at end of file +`endif diff --git a/include/zeroriscy_config.sv b/include/ibex_config.sv similarity index 95% rename from include/zeroriscy_config.sv rename to include/ibex_config.sv index 51012ecc..9afcee73 100644 --- a/include/zeroriscy_config.sv +++ b/include/ibex_config.sv @@ -16,7 +16,7 @@ // Davide Schiavone - pschiavo@iis.ee.ethz.ch // // // // Design Name: RISC-V config file // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Configure optional simulation modules // diff --git a/include/zeroriscy_defines.sv b/include/ibex_defines.sv similarity index 98% rename from include/zeroriscy_defines.sv rename to include/ibex_defines.sv index bea5bda6..e0cb7f80 100644 --- a/include/zeroriscy_defines.sv +++ b/include/ibex_defines.sv @@ -16,14 +16,14 @@ // // // // // Design Name: RISC-V processor core // -// Project Name: zero-riscy // +// Project Name: ibex // // Language: SystemVerilog // // // // Description: Defines for various constants used by the processor core. // // // //////////////////////////////////////////////////////////////////////////////// -package zeroriscy_defines; +package ibex_defines; //////////////////////////////////////////////// // ___ ____ _ // diff --git a/include/zeroriscy_tracer_defines.sv b/include/ibex_tracer_defines.sv similarity index 98% rename from include/zeroriscy_tracer_defines.sv rename to include/ibex_tracer_defines.sv index f2f1c4d4..b350c24c 100644 --- a/include/zeroriscy_tracer_defines.sv +++ b/include/ibex_tracer_defines.sv @@ -8,8 +8,8 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -package zeroriscy_tracer_defines; -import zeroriscy_defines::*; +package ibex_tracer_defines; +import ibex_defines::*; // instruction masks (for tracer) // parameter INSTR_CUSTOM0 = { 25'b?, OPCODE_CUST0 }; diff --git a/src_files.yml b/src_files.yml index 3427fa59..2426d7b8 100644 --- a/src_files.yml +++ b/src_files.yml @@ -1,28 +1,28 @@ -zeroriscy: +ibex: incdirs: [ include, ] files: [ - include/zeroriscy_defines.sv, - include/zeroriscy_tracer_defines.sv, - zeroriscy_alu.sv, - zeroriscy_compressed_decoder.sv, - zeroriscy_controller.sv, - zeroriscy_cs_registers.sv, - zeroriscy_debug_unit.sv, - zeroriscy_decoder.sv, - zeroriscy_int_controller.sv, - zeroriscy_ex_block.sv, - zeroriscy_id_stage.sv, - zeroriscy_if_stage.sv, - zeroriscy_load_store_unit.sv, - zeroriscy_multdiv_slow.sv, - zeroriscy_multdiv_fast.sv, - zeroriscy_prefetch_buffer.sv, - zeroriscy_fetch_fifo.sv, - zeroriscy_core.sv, + include/ibex_defines.sv, + include/ibex_tracer_defines.sv, + ibex_alu.sv, + ibex_compressed_decoder.sv, + ibex_controller.sv, + ibex_cs_registers.sv, + ibex_debug_unit.sv, + ibex_decoder.sv, + ibex_int_controller.sv, + ibex_ex_block.sv, + ibex_id_stage.sv, + ibex_if_stage.sv, + ibex_load_store_unit.sv, + ibex_multdiv_slow.sv, + ibex_multdiv_fast.sv, + ibex_prefetch_buffer.sv, + ibex_fetch_fifo.sv, + ibex_core.sv, ] -zeroriscy_vip_rtl: +ibex_vip_rtl: targets: [ rtl, ] @@ -30,11 +30,11 @@ zeroriscy_vip_rtl: include, ] files: [ - include/zeroriscy_defines.sv, - include/zeroriscy_tracer_defines.sv, - zeroriscy_tracer.sv, + include/ibex_defines.sv, + include/ibex_tracer_defines.sv, + ibex_tracer.sv, ] -zeroriscy_regfile_rtl: +ibex_regfile_rtl: targets: [ rtl, tsmc55, @@ -44,9 +44,9 @@ zeroriscy_regfile_rtl: include, ] files: [ - zeroriscy_register_file.sv, + ibex_register_file.sv, ] -zeroriscy_regfile_fpga: +ibex_regfile_fpga: targets: [ xilinx, ] @@ -54,6 +54,6 @@ zeroriscy_regfile_fpga: include, ] files: [ - zeroriscy_register_file_ff.sv, + ibex_register_file_ff.sv, ]