diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile
index 0c901ba1..780279f9 100644
--- a/dv/uvm/core_ibex/Makefile
+++ b/dv/uvm/core_ibex/Makefile
@@ -46,6 +46,7 @@ IBEX_CONFIG         := opentitan
 all: collect_results $(if $(filter 1,$(COV)),merge_cov,)
 
 # Build Stages
+.PHONY: core_config
 .PHONY: instr_gen_build
 .PHONY: instr_gen_run
 .PHONY: instr_gen_compile
@@ -103,15 +104,6 @@ clean:
 	rm -f $(EXT_DIR)/riscv_core_setting.sv
 	rm -rf $(OUT-DIR)
 
-.PHONY: core_config
-core_config:
-	@cp $(EXT_DIR)/riscv_core_setting.sv.default $(EXT_DIR)/riscv_core_setting.sv
-	@if [[ "$(IBEX_CONFIG)" == "small" ]] || \
-	    [[ "$(IBEX_CONFIG)" == "experimental-branch-predictor" ]]; \
-	then \
-	  patch -u $(EXT_DIR)/riscv_core_setting.sv -i $(EXT_DIR)/riscv_core_setting.nopmp.sv.patch; \
-	fi
-
 ###############################################################################
 # Setup the metadata for the regression, which can then be accessed by
 # all python scripts and testcases
@@ -159,6 +151,10 @@ comp-results = $(addsuffix trr.yaml,$(ts-dirs))
 rtl-sim-logfile := rtl_sim.log
 
 ###
+CORE-CONFIG-STAMP = $(METADATA-DIR)/core.config.stamp
+core_config: $(CORE-CONFIG-STAMP)
+core-config-var-deps := IBEX_CONFIG
+
 INSTR-GEN-BUILD-STAMP = $(METADATA-DIR)/instr.gen.build.stamp
 instr_gen_build: $(METADATA-DIR)/instr.gen.build.stamp
 instr-gen-build-var-deps := SIMULATOR SIGNATURE_ADDR  # Rebuild if these change
@@ -248,8 +244,24 @@ instr-gen-build-vars-prereq = \
 # Finally, $(instr-gen-build-vars-prereq) becomes a dependency of our target.
 ################## END EXAMPLE ###################
 
+core-config-vars-path := $(BUILD-DIR)/.cc.vars.mk
+-include $(core-config-vars-path)
+
+core-config-var-prereq = $(call vars-prereq,gen,Generate core configuration file,$(core-config-var-deps))
+$(CORE-CONFIG-STAMP): \
+  $(core-config-var-prereq) ./riscv_dv_extension/riscv_core_setting.tpl.sv \
+  scripts/render_config_template.py \
+  | $(BUILD-DIR)
+	@echo Generating core configuration file
+	$(verb)env PYTHONPATH=$(PYTHONPATH) \
+	  scripts/render_config_template.py \
+	    --dir-metadata $(METADATA-DIR) \
+	    $(EXT_DIR)/riscv_core_setting.tpl.sv > $(EXT_DIR)/riscv_core_setting.sv
+	$(call dump-vars,$(core-config-vars-path),gen,$(core-config-var-deps))
+	@touch $@
+
 $(METADATA-DIR)/instr.gen.build.stamp: \
-  $(instr-gen-build-vars-prereq) $(riscv-dv-files) core_config \
+  $(instr-gen-build-vars-prereq) $(riscv-dv-files) $(CORE-CONFIG-STAMP) \
   scripts/build_instr_gen.py \
   | $(BUILD-DIR)
 	@echo Building randomized test generator
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.nopmp.sv.patch b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.nopmp.sv.patch
deleted file mode 100644
index ad25ed8f..00000000
--- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.nopmp.sv.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- riscv_core_setting.sv.default	2022-07-15 12:35:52.670143953 +0100
-+++ riscv_core_setting.sv.small	2022-07-15 12:38:04.071391739 +0100
-@@ -63,10 +63,10 @@
- int max_interrupt_vector_num = 32;
- 
- // Physical memory protection support
--bit support_pmp = 1;
-+bit support_pmp = 0;
- 
- // Enhanced physical memory protection support
--bit support_epmp = 1;
-+bit support_epmp = 0;
- 
- // Debug mode support
- bit support_debug_mode = 1;
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv.default b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
similarity index 97%
rename from dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv.default
rename to dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
index e3da061c..cc8df8b2 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv.default
+++ b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
@@ -62,11 +62,19 @@ mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};
 // supported
 int max_interrupt_vector_num = 32;
 
+% if ibex_config['PMPEnable']:
 // Physical memory protection support
 bit support_pmp = 1;
 
 // Enhanced physical memory protection support
 bit support_epmp = 1;
+% else:
+// Physical memory protection support
+bit support_pmp = 0;
+
+// Enhanced physical memory protection support
+bit support_epmp = 0;
+% endif
 
 // Debug mode support
 bit support_debug_mode = 1;
diff --git a/dv/uvm/core_ibex/scripts/render_config_template.py b/dv/uvm/core_ibex/scripts/render_config_template.py
new file mode 100755
index 00000000..7e2fb56a
--- /dev/null
+++ b/dv/uvm/core_ibex/scripts/render_config_template.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import pathlib3x as pathlib
+from mako.template import Template
+
+from metadata import LockedMetadata, RegressionMetadata
+from ibex_cmd import get_config
+
+
+def render_template(config_name: str, template_filename: str) -> str:
+    ibex_config_template = Template(filename=template_filename)
+    ibex_config = get_config(config_name)
+    return ibex_config_template.render(ibex_config=ibex_config.params)
+
+
+def _main():
+    """Renders a mako template providing parameters from the metadata ibex
+    config
+    """
+    parser = argparse.ArgumentParser()
+    parser.add_argument('template_filename')
+    parser.add_argument('--dir-metadata', type=pathlib.Path, required=True)
+    args = parser.parse_args()
+
+    with LockedMetadata(args.dir_metadata, __file__) as md:
+        print(render_template(md.ibex_config, args.template_filename))
+
+
+if __name__ == "__main__":
+    _main()