diff --git a/dv/uvm/ibex_dv.f b/dv/uvm/ibex_dv.f
index 2ee06d27..410d85f1 100644
--- a/dv/uvm/ibex_dv.f
+++ b/dv/uvm/ibex_dv.f
@@ -6,7 +6,7 @@
 +define+TRACE_EXECUTION
 +define+RVFI
 
-${PRJ_DIR}/ibex/dv/uvm/tb/prim_clock_gating.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_clock_gating.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/ibex/rtl
diff --git a/dv/uvm/tb/prim_clock_gating.sv b/dv/uvm/tb/prim_clock_gating.sv
deleted file mode 100644
index b27bc36a..00000000
--- a/dv/uvm/tb/prim_clock_gating.sv
+++ /dev/null
@@ -1,26 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Dummy clock gating module compatible with latch-based register file
-
-module prim_clock_gating #(
-    parameter string Impl = "default"
-) (
-    input        clk_i,
-    input        en_i,
-    input        test_en_i,
-    output logic clk_o
-);
-
-  logic clk_en;
-
-  always_latch begin
-    if (clk_i == 1'b0) begin
-      clk_en <= en_i | test_en_i;
-    end
-  end
-
-  assign clk_o = clk_i & clk_en;
-
-endmodule
diff --git a/ibex_core.core b/ibex_core.core
index d30b635e..d0ad72c5 100644
--- a/ibex_core.core
+++ b/ibex_core.core
@@ -30,8 +30,8 @@ filesets:
     file_type: systemVerilogSource
 
   files_lint:
-    files:
-      - dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
+    depend:
+      - lowrisc:ibex:sim_shared
 
   files_lint_verilator:
     files:
diff --git a/ibex_core_tracing.core b/ibex_core_tracing.core
index 84ca758b..7b8f4afa 100644
--- a/ibex_core_tracing.core
+++ b/ibex_core_tracing.core
@@ -14,8 +14,8 @@ filesets:
     file_type: systemVerilogSource
 
   files_lint:
-    files:
-      - dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
+    depend:
+      - lowrisc:ibex:sim_shared
 
   files_lint_verilator:
     files:
diff --git a/shared/rtl/prim_clock_gating.sv b/shared/rtl/prim_clock_gating.sv
index ed13f44c..a5b81380 100644
--- a/shared/rtl/prim_clock_gating.sv
+++ b/shared/rtl/prim_clock_gating.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Dummy clock gating module
+// Dummy clock gating module compatible with latch-based register file
 
 module prim_clock_gating (
     input        clk_i,