diff --git a/dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv b/dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv
new file mode 100644
index 00000000..92d36791
--- /dev/null
+++ b/dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Abstract primitives wrapper.
+//
+// This file is a stop-gap until the DV file list is generated by FuseSoC.
+// Its contents are taken from the file which would be generated by FuseSoC.
+// https://github.com/lowRISC/ibex/issues/893
+
+module prim_clock_mux2 #(
+  parameter bit NoFpgaBufG = 1'b0
+) (
+  input        clk0_i,
+  input        clk1_i,
+  input        sel_i,
+  output logic clk_o
+);
+
+if (1) begin : gen_generic
+  prim_generic_clock_mux2 #(
+    .NoFpgaBufG(NoFpgaBufG)
+  ) u_impl_generic (
+    .*
+  );
+end
+
+endmodule
diff --git a/dv/uvm/core_ibex/common/prim/prim_flop.sv b/dv/uvm/core_ibex/common/prim/prim_flop.sv
new file mode 100644
index 00000000..52e982a2
--- /dev/null
+++ b/dv/uvm/core_ibex/common/prim/prim_flop.sv
@@ -0,0 +1,30 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Abstract primitives wrapper.
+//
+// This file is a stop-gap until the DV file list is generated by FuseSoC.
+// Its contents are taken from the file which would be generated by FuseSoC.
+// https://github.com/lowRISC/ibex/issues/893
+
+module prim_flop #(
+  parameter int               Width      = 1,
+  parameter logic [Width-1:0] ResetValue = 0
+) (
+  input                    clk_i,
+  input                    rst_ni,
+  input        [Width-1:0] d_i,
+  output logic [Width-1:0] q_o
+);
+
+if (1) begin : gen_generic
+  prim_generic_flop #(
+    .ResetValue(ResetValue),
+    .Width(Width)
+  ) u_impl_generic (
+    .*
+  );
+end
+
+endmodule
diff --git a/dv/uvm/core_ibex/ibex_dv.f b/dv/uvm/core_ibex/ibex_dv.f
index c8efc8fb..4cee39c3 100644
--- a/dv/uvm/core_ibex/ibex_dv.f
+++ b/dv/uvm/core_ibex/ibex_dv.f
@@ -37,6 +37,10 @@ ${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
 ${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_buf.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
+${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_clock_mux2.sv
+${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
+${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_flop.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/rtl
diff --git a/ibex_top.core b/ibex_top.core
index 8979a2f4..234311ec 100644
--- a/ibex_top.core
+++ b/ibex_top.core
@@ -11,6 +11,8 @@ filesets:
       - lowrisc:ibex:ibex_pkg
       - lowrisc:ibex:ibex_core
       - lowrisc:prim:buf
+      - lowrisc:prim:clock_mux2
+      - lowrisc:prim:flop
     files:
       - rtl/ibex_register_file_ff.sv # generic FF-based
       - rtl/ibex_register_file_fpga.sv # FPGA
diff --git a/rtl/ibex_lockstep.sv b/rtl/ibex_lockstep.sv
index f56ae3b9..bbd07ba0 100644
--- a/rtl/ibex_lockstep.sv
+++ b/rtl/ibex_lockstep.sv
@@ -128,16 +128,33 @@ module ibex_lockstep import ibex_pkg::*; #(
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       rst_shadow_cnt_q <= '0;
-      rst_shadow_set_q <= '0;
       enable_cmp_q     <= '0;
     end else begin
       rst_shadow_cnt_q <= rst_shadow_cnt_d;
-      rst_shadow_set_q <= rst_shadow_set_d;
       enable_cmp_q     <= rst_shadow_set_q;
     end
   end
 
-  assign rst_shadow_n = test_en_i ? scan_rst_ni : rst_shadow_set_q;
+  // The primitives below are used to place size-only constraints in order to prevent
+  // synthesis optimizations and preserve anchor points for constraining backend tools.
+  prim_flop #(
+    .Width(1),
+    .ResetValue(1'b0)
+  ) u_prim_rst_shadow_set_flop (
+    .clk_i (clk_i),
+    .rst_ni(rst_ni),
+    .d_i   (rst_shadow_set_d),
+    .q_o   (rst_shadow_set_q)
+  );
+
+  prim_clock_mux2 #(
+    .NoFpgaBufG(1'b1)
+  ) u_prim_rst_shadow_n_mux2 (
+    .clk0_i(rst_shadow_set_q),
+    .clk1_i(scan_rst_ni),
+    .sel_i (test_en_i),
+    .clk_o (rst_shadow_n)
+  );
 
   //////////////////
   // Input delays //