diff --git a/hwloop_controller.sv b/hwloop_controller.sv
index 7975d139..6c295252 100644
--- a/hwloop_controller.sv
+++ b/hwloop_controller.sv
@@ -73,10 +73,11 @@ module riscv_hwloop_controller
     hwlp_targ_addr_o = 'x;
     hwlp_dec_cnt_o   = '0;
 
-    for (j = N_REGS-1; j >= 0; j--) begin
+    for (j = 0; j < N_REGS; j++) begin
       if (pc_is_end_addr[j]) begin
         hwlp_targ_addr_o  = hwlp_start_addr_i[j];
         hwlp_dec_cnt_o[j] = 1'b1;
+        break;
       end
     end
   end
diff --git a/hwloop_regs.sv b/hwloop_regs.sv
index a956baaf..bba508b7 100644
--- a/hwloop_regs.sv
+++ b/hwloop_regs.sv
@@ -115,18 +115,27 @@ module riscv_hwloop_regs
     begin
       hwlp_counter_q <= '{default: 32'b0};
     end
-    else if (hwlp_we_i[2] == 1'b1) // potential contention problem here!
-    begin
-      hwlp_counter_q[hwlp_regid_i] <= hwlp_cnt_data_i;
-    end
     else
     begin
-      for (i = 0; i < N_REGS; i++)
+      if (hwlp_we_i[2] == 1'b1) // potential contention problem here!
       begin
-        if (hwlp_dec_cnt_i[i] && valid_i)
-          hwlp_counter_q[i] <= hwlp_counter_n;
+        hwlp_counter_q[hwlp_regid_i] <= hwlp_cnt_data_i;
+      end else begin
+        for (i = 0; i < N_REGS; i++)
+        begin
+          if (hwlp_dec_cnt_i[i] && valid_i)
+            hwlp_counter_q[i] <= hwlp_counter_n[i];
+        end
       end
     end
   end
 
+  //----------------------------------------------------------------------------
+  // Assertions
+  //----------------------------------------------------------------------------
+
+  // do not decrement more than one counter at once
+  assert property (
+    @(posedge clk) (valid_i) |-> ($countones(hwlp_dec_cnt_i) <= 1) );
+
 endmodule