From 46fe850b05a9ba2921890e1468396d5a60a58b49 Mon Sep 17 00:00:00 2001 From: Pasquale Davide Schiavone Date: Fri, 27 Jan 2017 16:16:13 +0100 Subject: [PATCH] update tracer and elw --- controller.sv | 1 + id_stage.sv | 2 +- littleriscv_core.sv | 9 ++++----- riscv_tracer.sv | 13 ++++++++++--- 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/controller.sv b/controller.sv index d5ae6136..1d029fa4 100644 --- a/controller.sv +++ b/controller.sv @@ -247,6 +247,7 @@ module littleriscv_controller DECODE: begin + //TODO: define interrupt during sw/lw is_decoding_o = 1'b0; // decode and execute instructions only if the current conditional diff --git a/id_stage.sv b/id_stage.sv index aab170c5..cd331efa 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -664,7 +664,7 @@ module littleriscv_id_stage data_req_ex_o = data_req_id; data_reg_offset_ex_o = data_reg_offset_id; - data_load_event_ex_o = ((data_req_id & (~halt_id) & wb_ready_i) ? data_load_event_id : 1'b0); + data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0); branch_in_ex_o = (jump_in_dec == BRANCH_COND); end diff --git a/littleriscv_core.sv b/littleriscv_core.sv index 38219456..d4817d14 100644 --- a/littleriscv_core.sv +++ b/littleriscv_core.sv @@ -687,7 +687,7 @@ module littleriscv_core .ex_reg_addr ( id_stage_i.regfile_waddr_mux ), .ex_reg_we ( id_stage_i.regfile_we_mux ), .ex_reg_wdata ( id_stage_i.regfile_wdata_mux ), - + .data_valid_lsu ( data_valid_lsu ), .ex_data_addr ( data_addr_o ), .ex_data_req ( data_req_o ), .ex_data_gnt ( data_gnt_i ), @@ -697,9 +697,9 @@ module littleriscv_core .wb_bypass ( branch_in_ex_o ), - .wb_valid ( data_valid_lsu ), - .wb_reg_addr ( ), - .wb_reg_we ( ), + .wb_valid ( ), + .wb_reg_addr ( ), + .wb_reg_we ( ), .wb_reg_wdata ( regfile_wdata_lsu ), .imm_u_type ( id_stage_i.imm_u_type ), @@ -750,7 +750,6 @@ module littleriscv_core .ex_reg_we ( id_stage_i.registers_i.we_a_i ), .ex_reg_wdata ( id_stage_i.registers_i.wdata_b_i ), - .data_valid_lsu ( data_valid_lsu ) .ex_data_addr ( data_addr_o ), .ex_data_req ( data_req_o ), .ex_data_gnt ( data_gnt_i ), diff --git a/riscv_tracer.sv b/riscv_tracer.sv index bc5845e9..fa47ea87 100644 --- a/riscv_tracer.sv +++ b/riscv_tracer.sv @@ -712,7 +712,14 @@ module littleriscv_tracer trace.regs_write[i].value = ex_reg_wdata; end // look for data accesses and log them - if (ex_data_req && ex_data_gnt) begin + if (ex_data_req) begin + + if(~ex_data_gnt) begin + //we wait until the the gnt comes + do @(negedge clk); + while (!ex_data_gnt); + end + mem_acc.addr = ex_data_addr; mem_acc.we = ex_data_we; @@ -720,15 +727,15 @@ module littleriscv_tracer mem_acc.wdata = ex_data_wdata; else mem_acc.wdata = 'x; - - trace.mem_access.push_back(mem_acc); //we wait until the the data instruction ends do @(negedge clk); while (!data_valid_lsu); + if (~mem_acc.we) //load operations foreach(trace.regs_write[i]) trace.regs_write[i].value = wb_reg_wdata; + trace.mem_access.push_back(mem_acc); end trace.printInstrTrace();