diff --git a/vendor/riscv-arch-tests/CHANGELOG.md b/vendor/riscv-arch-tests/CHANGELOG.md
index 2f0e3f5e..3a3d8e6a 100644
--- a/vendor/riscv-arch-tests/CHANGELOG.md
+++ b/vendor/riscv-arch-tests/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.6.2] - 2023-02-08
+- Remove RV64IB from ISA list of zext test. 
+
 ## [3.6.1] - 2023-01-28
 - Fix satp restore condition.
 
diff --git a/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h b/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
index 8223f9ab..d731973f 100644
--- a/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
+++ b/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
@@ -86,6 +86,7 @@
 
 #include "encoding.h"
 #include "test_macros.h"
+#define XLEN __riscv_xlen
 #define MIN(a,b) (((a)<(b))?(a):(b))
 #define MAX(a,b) (((a)>(b))?(a):(b))
 #define BIT(addr, bit) (((addr)>>(bit))&1)
@@ -104,8 +105,6 @@
 #define LIMMSZ     (WDBITS-IMMSZ)
 #define LIMMMSK    ( (1 <<LIMMSZ)-1)
 
-#define XLEN __riscv_xlen
-
 #define ALIGNSZ ((XLEN>>5)+2)   // log2(XLEN): 2,3,4 for XLEN 32,64,128
 #if XLEN>FLEN
   #define SIGALIGN REGWIDTH
diff --git a/vendor/riscv_arch_tests.lock.hjson b/vendor/riscv_arch_tests.lock.hjson
index b69f8a96..ac9480bf 100644
--- a/vendor/riscv_arch_tests.lock.hjson
+++ b/vendor/riscv_arch_tests.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/riscv-non-isa/riscv-arch-test
-    rev: 89fbfec7f67fedfbbcf6de374e32c902669317e9
+    rev: a3b7f0c2cf89652b8a0cba3146890c512ff8ba44
   }
 }
diff --git a/vendor/riscv_arch_tests.vendor.hjson b/vendor/riscv_arch_tests.vendor.hjson
index ba900a82..061f85c3 100644
--- a/vendor/riscv_arch_tests.vendor.hjson
+++ b/vendor/riscv_arch_tests.vendor.hjson
@@ -14,5 +14,9 @@
     "riscv-test-suite/rv32i_m/D",
     "riscv-test-suite/rv32i_m/F",
     "riscv-test-suite/rv64i_m",
+    "riscv-test-suite/rv32i_m/B/src/sext.b-01.S",
+    "riscv-test-suite/rv32i_m/B/src/sext.h-01.S",
+    "riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S"
   ]
+  patch_dir: "patches/riscv_arch_tests"
 }