From 498786aef586f3643fdb9c5e02c46db9a4a056d4 Mon Sep 17 00:00:00 2001
From: udinator <udij@google.com>
Date: Mon, 4 Nov 2019 13:41:36 -0800
Subject: [PATCH] Update google_riscv-dv to google/riscv-dv@44bec76 (#447)

Update code from upstream repository https://github.com/google/riscv-
dv to revision 44bec7695fd2399166e181fa84b66a608b5f745f

* Re-enable custom OVPsim configuration files (google/riscv-dv#282)
  (udinator)
---
 vendor/google_riscv-dv.lock.hjson    | 2 +-
 vendor/google_riscv-dv/run.py        | 5 ++++-
 vendor/google_riscv-dv/yaml/iss.yaml | 2 +-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/vendor/google_riscv-dv.lock.hjson b/vendor/google_riscv-dv.lock.hjson
index d58f72fd..6bccab75 100644
--- a/vendor/google_riscv-dv.lock.hjson
+++ b/vendor/google_riscv-dv.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/google/riscv-dv
-    rev: cce71d24b56f641d994fbf69b8b50aa3756b9322
+    rev: 44bec7695fd2399166e181fa84b66a608b5f745f
   }
 }
diff --git a/vendor/google_riscv-dv/run.py b/vendor/google_riscv-dv/run.py
index d8cd3b75..2902c0ab 100644
--- a/vendor/google_riscv-dv/run.py
+++ b/vendor/google_riscv-dv/run.py
@@ -93,7 +93,10 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir):
       logging.info("Found matching ISS: %s" % entry['iss'])
       cmd = entry['cmd'].rstrip()
       cmd = re.sub("\<path_var\>", get_env_var(entry['path_var']), cmd)
-      cmd = re.sub("\<variant\>", isa, cmd)
+      if iss == "ovpsim":
+        cmd = re.sub("\<cfg_path\>", setting_dir, cmd)
+      else:
+        cmd = re.sub("\<variant\>", isa, cmd)
       return cmd
   logging.error("Cannot find ISS %0s" % iss)
   sys.exit(1)
diff --git a/vendor/google_riscv-dv/yaml/iss.yaml b/vendor/google_riscv-dv/yaml/iss.yaml
index 30a882a9..5677ef01 100644
--- a/vendor/google_riscv-dv/yaml/iss.yaml
+++ b/vendor/google_riscv-dv/yaml/iss.yaml
@@ -21,7 +21,7 @@
   path_var: OVPSIM_PATH
   cmd: >
     <path_var>/riscvOVPsim.exe
-    --controlfile target/<variant>/riscvOVPsim.ic
+    --controlfile <cfg_path>/riscvOVPsim.ic
     --objfilenoentry <elf>
     --override riscvOVPsim/cpu/PMP_registers=0
     --override riscvOVPsim/cpu/simulateexceptions=T