diff --git a/doc/02_user/examples.rst b/doc/02_user/examples.rst index ef9007f2..8a89bb03 100644 --- a/doc/02_user/examples.rst +++ b/doc/02_user/examples.rst @@ -3,16 +3,25 @@ Examples ======== -To make use of Ibex it has to be integrated as described in :ref:`core-integration`. +There are two examples that demonstrate Ibex usage. -FPGA ----- +The first is 'Simple System' and is part of the Ibex repository. +It demonstrates a minimal system connecting Ibex to some memory with a timer peripheral and is targeted at simulation. -A minimal example for the `Arty A7 `_ FPGA Development board is provided. -In this example Ibex is directly linked to a SRAM memory instance. -Four LEDs from the board are connected to the data bus and are updated each time when a word is written. -The memory is separated into a instruction and data section. -The instructions memory is initialized at synthesis time by reading the output from the software build. -The software writes to the data section the complementary lower for bits of a word every second resulting in blinking LEDs. +The second is the `'Ibex Demo System' `_ which is a separate repository. +It is targeted at FPGA implementation and contains some extra peripherals along with a RISC-V debug module integration. + +Simple System +------------- + +Simple system is built via FuseSoC. +Verilator is the primary simulator it is designed for, though other simulators are also supported (such as VCS). +Its aim is to make running a binary against Ibex RTL, obtaining an instruction trace, wave trace and any other simulation outputs as simple as possible along with demonstrating basic Ibex integration. +See the `Simple System README `_ for more information. + +There is an extended version of simple system which adds co-simulation checking. +This cross-checks every instruction execution against a RISC-V ISS. +It is the same co-simulation method used by our full DV environment but enables its use in a far simpler setup. +The simple system co-simulation setup is compatible with Verilator (unlike our full DV environment). +See :ref:`cosim` for more information. -Find the description of how to build and program the Arty board in ``examples/fpga/artya7/README.md``.