diff --git a/vendor/patches/riscv_arch_tests/xlen_change.patch b/vendor/patches/riscv_arch_tests/xlen_change.patch
new file mode 100644
index 00000000..0851ddb3
--- /dev/null
+++ b/vendor/patches/riscv_arch_tests/xlen_change.patch
@@ -0,0 +1,12 @@
+diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
+index e542123b9..d731973fd 100644
+--- a/riscv-test-suite/env/arch_test.h
++++ b/riscv-test-suite/env/arch_test.h
+@@ -86,6 +86,7 @@
+ 
+ #include "encoding.h"
+ #include "test_macros.h"
++#define XLEN __riscv_xlen
+ #define MIN(a,b) (((a)<(b))?(a):(b))
+ #define MAX(a,b) (((a)>(b))?(a):(b))
+ #define BIT(addr, bit) (((addr)>>(bit))&1)
diff --git a/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h b/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
index e542123b..8223f9ab 100644
--- a/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
+++ b/vendor/riscv-arch-tests/riscv-test-suite/env/arch_test.h
@@ -104,6 +104,8 @@
 #define LIMMSZ     (WDBITS-IMMSZ)
 #define LIMMMSK    ( (1 <<LIMMSZ)-1)
 
+#define XLEN __riscv_xlen
+
 #define ALIGNSZ ((XLEN>>5)+2)   // log2(XLEN): 2,3,4 for XLEN 32,64,128
 #if XLEN>FLEN
   #define SIGALIGN REGWIDTH