diff --git a/alu.sv b/alu.sv
index cc0f3bb9..1f50b7f7 100644
--- a/alu.sv
+++ b/alu.sv
@@ -536,7 +536,7 @@ module riscv_alu
     shift_left = 1'b0;
     shift_amt  = operand_b_i;
     result_o   = 'x;
-    flag_o     = 1'b0;
+    flag_o     = 1'bx;
 
     unique case (operator_i)
       // Standard Operations
diff --git a/controller.sv b/controller.sv
index f09ea3e5..6ce67932 100644
--- a/controller.sv
+++ b/controller.sv
@@ -539,4 +539,9 @@ module riscv_controller
   assign perf_jr_stall_o  = jr_stall_o;
   assign perf_ld_stall_o  = load_stall_o;
 
+
+  // Assertions
+  assert property (
+    @(posedge clk) (pc_mux_sel_o == `PC_BRANCH) |-> (branch_decision_i !== 1'bx) );
+
 endmodule // controller