diff --git a/dv/cs_registers/tb_cs_registers.core b/dv/cs_registers/tb_cs_registers.core
index 0c1b63fa..7cfad6ef 100644
--- a/dv/cs_registers/tb_cs_registers.core
+++ b/dv/cs_registers/tb_cs_registers.core
@@ -104,6 +104,7 @@ targets:
     tools:
       vcs:
         vcs_options:
+          - '-xlrm uniq_prior_final'
           - '../src/lowrisc_ibex_tb_cs_registers_0/build/bin/reg_dpi.so'
           - '-debug_access+all'
 
diff --git a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index 7198bd7f..cc7eee6c 100644
--- a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -24,6 +24,7 @@
          -Mdir=<out>/vcs_simv.csrc
          -o <out>/vcs_simv
          -debug_access+pp
+         -xlrm uniq_prior_final
          -lca -kdb <cmp_opts> <wave_opts> <cov_opts>"
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
diff --git a/examples/simple_system/ibex_simple_system.core b/examples/simple_system/ibex_simple_system.core
index d8114e4f..d3127a87 100644
--- a/examples/simple_system/ibex_simple_system.core
+++ b/examples/simple_system/ibex_simple_system.core
@@ -76,6 +76,7 @@ targets:
     tools:
       vcs:
         vcs_options:
+          - '-xlrm uniq_prior_final'
           - '-debug_access+r'
       verilator:
         mode: cc