diff --git a/dv/uvm/tb/core_ibex_tb_top.sv b/dv/uvm/tb/core_ibex_tb_top.sv
index aa15488f..f2986b64 100644
--- a/dv/uvm/tb/core_ibex_tb_top.sv
+++ b/dv/uvm/tb/core_ibex_tb_top.sv
@@ -26,7 +26,6 @@ module core_ibex_tb_top;
   // CSR access interface
   core_ibex_csr_if csr_if(.clk(clk));
 
-  // TODO(taliu) Resolve the tied-off ports
   ibex_core_tracing #(.DmHaltAddr(`BOOT_ADDR + 'h0),
                       .DmExceptionAddr(`BOOT_ADDR + 'h4)) dut (
     .clk_i(clk),
diff --git a/dv/uvm/tests/core_ibex_base_test.sv b/dv/uvm/tests/core_ibex_base_test.sv
index 181a6e14..5c316507 100644
--- a/dv/uvm/tests/core_ibex_base_test.sv
+++ b/dv/uvm/tests/core_ibex_base_test.sv
@@ -107,11 +107,6 @@ class core_ibex_base_test extends uvm_test;
   endfunction
 
   virtual task wait_for_test_done();
-    // TODO(taliu): We need a consistent approach to determine the test is completed for both
-    // random instruction test and firmware based test. For example, it could be done by writing to
-    // a specific memory location of the test signature. Right now the random instruction generator
-    // use ecall instruction to indicate the end of the program. It could be changed to align with
-    // firmware test completion mechanism.
     fork
       begin
         wait (dut_vif.ecall === 1'b1);
diff --git a/dv/uvm/tests/core_ibex_test_lib.sv b/dv/uvm/tests/core_ibex_test_lib.sv
index 143b3e54..b90e1534 100644
--- a/dv/uvm/tests/core_ibex_test_lib.sv
+++ b/dv/uvm/tests/core_ibex_test_lib.sv
@@ -444,8 +444,6 @@ class core_ibex_debug_wfi_test extends core_ibex_directed_test;
   `uvm_component_new
 
   virtual task check_stimulus();
-    // TODO(udi) - need to check that no other instruction fetches occur after after the WFI
-    // is detected, and before any stimulus is sent to the core
     forever begin
       wait (dut_vif.wfi === 1'b1);
       wait (dut_vif.core_sleep === 1'b1);
@@ -649,7 +647,6 @@ class core_ibex_mem_error_test extends core_ibex_directed_test;
   int err_delay;
 
   // check memory error inputs and verify that core jumps to correct exception handler
-  // TODO(udinator) - add checks for the RVFI interface
   virtual task check_stimulus();
     forever begin
       while (!vseq.data_intf_seq.get_error_synch()) begin