diff --git a/controller.sv b/controller.sv
index b90fca5f..a5e38e03 100644
--- a/controller.sv
+++ b/controller.sv
@@ -77,7 +77,6 @@ module riscv_controller
 
   input  logic        trap_hit_i,                 // a trap was hit, so we have to flush EX and WB
 
-  output logic        save_pc_if_o,
   output logic        save_pc_id_o,
 
   // Debug Unit Signals
@@ -165,7 +164,6 @@ module riscv_controller
     instr_req_o   = 1'b1;
 
     exc_ack_o     = 1'b0;
-    save_pc_if_o  = 1'b0;
     save_pc_id_o  = 1'b0;
 
     pc_mux_o      = `PC_BOOT;
diff --git a/cs_registers.sv b/cs_registers.sv
index 040aa91e..856fc528 100644
--- a/cs_registers.sv
+++ b/cs_registers.sv
@@ -49,9 +49,7 @@ module riscv_cs_registers
   output logic        irq_enable_o,
   output logic [31:0] epcr_o,
 
-  input  logic [31:0] curr_pc_if_i,
   input  logic [31:0] curr_pc_id_i,
-  input  logic        save_pc_if_i,
   input  logic        save_pc_id_i,
 
   input  logic [5:0]  exc_cause_i,
@@ -222,9 +220,7 @@ module riscv_cs_registers
       exc_cause  <= exc_cause_n;
 
       // exception controller gets priority over other writes
-      if (save_pc_if_i == 1'b1)
-        csr[`CSR_IDX_MEPC] <= curr_pc_if_i;
-      else if (save_pc_id_i == 1'b1)
+      if (save_pc_id_i == 1'b1)
         csr[`CSR_IDX_MEPC] <= curr_pc_id_i;
 
       if (save_exc_cause_i)
diff --git a/id_stage.sv b/id_stage.sv
index 08f18322..ba52455b 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -137,7 +137,6 @@ module riscv_id_stage
     output logic [5:0]  exc_cause_o,
     output logic        save_exc_cause_o,
 
-    output logic        save_pc_if_o,
     output logic        save_pc_id_o,
 
     input  logic        lsu_load_err_i,
@@ -668,7 +667,6 @@ module riscv_id_stage
     .trap_hit_i                     ( trap_hit               ),
 
     .save_pc_id_o                   ( save_pc_id_o           ),
-    .save_pc_if_o                   ( save_pc_if_o           ),
 
     // Debug Unit Signals
     .dbg_stall_i                    ( dbg_stall_i            ),
diff --git a/riscv_core.sv b/riscv_core.sv
index 5e95fec3..cc459497 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -190,7 +190,6 @@ module riscv_core
 
   logic [5:0]  exc_cause;
   logic        save_exc_cause;
-  logic        save_pc_if;
   logic        save_pc_id;
 
 
@@ -410,7 +409,6 @@ module riscv_core
     .irq_enable_i                 ( irq_enable           ), // global interrupt enable
     .exc_cause_o                  ( exc_cause            ),
     .save_exc_cause_o             ( save_exc_cause       ),
-    .save_pc_if_o                 ( save_pc_if           ), // control signal to save pc
     .save_pc_id_o                 ( save_pc_id           ), // control signal to save pc
     .lsu_load_err_i               ( lsu_load_err         ),
     .lsu_store_err_i              ( lsu_store_err        ),
@@ -597,9 +595,7 @@ module riscv_core
     .irq_enable_o            ( irq_enable     ),
     .epcr_o                  ( epcr           ),
 
-    .curr_pc_if_i            ( current_pc_if  ),    // from IF stage
     .curr_pc_id_i            ( current_pc_id  ),    // from IF stage
-    .save_pc_if_i            ( save_pc_if     ),
     .save_pc_id_i            ( save_pc_id     ),
 
     .exc_cause_i             ( exc_cause      ),