diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
index 0f43faef..33056ae5 100644
--- a/rtl/ibex_core.sv
+++ b/rtl/ibex_core.sv
@@ -386,7 +386,7 @@ module ibex_core #(
   // main clock gate of the core
   // generates all clocks except the one for the debug unit which is
   // independent
-  prim_clock_gating core_clock_gate_i (
+  cluster_clock_gating core_clock_gate_i (
       .clk_i     ( clk_i           ),
       .en_i      ( clock_en        ),
       .test_en_i ( test_en_i       ),
diff --git a/rtl/ibex_register_file_latch.sv b/rtl/ibex_register_file_latch.sv
index 8c5fb35b..4b5816d5 100644
--- a/rtl/ibex_register_file_latch.sv
+++ b/rtl/ibex_register_file_latch.sv
@@ -67,7 +67,7 @@ module ibex_register_file_latch #(
   // WRITE //
   ///////////
   // Global clock gating
-  prim_clock_gating cg_we_global (
+  cluster_clock_gating cg_we_global (
       .clk_i     ( clk_i     ),
       .en_i      ( we_a_i    ),
       .test_en_i ( test_en_i ),
@@ -99,7 +99,7 @@ module ibex_register_file_latch #(
 
   // Individual clock gating (if integrated clock-gating cells are available)
   for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
-    prim_clock_gating cg_i (
+    cluster_clock_gating cg_i (
         .clk_i     ( clk_int           ),
         .en_i      ( waddr_onehot_a[x] ),
         .test_en_i ( test_en_i         ),
@@ -129,7 +129,7 @@ module ibex_register_file_latch #(
     assign we_r0_dummy = we_a_i & dummy_instr_id_i;
 
     // R0 clock gate
-    prim_clock_gating cg_i (
+    cluster_clock_gating cg_i (
         .clk_i     ( clk_int     ),
         .en_i      ( we_r0_dummy ),
         .test_en_i ( test_en_i   ),