diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile
index 9e7cf2f2..57d73b1a 100644
--- a/dv/uvm/core_ibex/Makefile
+++ b/dv/uvm/core_ibex/Makefile
@@ -40,6 +40,8 @@ OUT-SEED := $(OUT)/seed-$(SEED)
 export dv_root := $(realpath ../../../vendor/lowrisc_ip/dv)
 export DUT_TOP := dut
 
+# Compile time options for ibex RTL simulation
+COMPILE_OPTS        +=
 # Run time options for ibex RTL simulation
 SIM_OPTS            :=
 # Enable waveform dumping
@@ -157,6 +159,7 @@ include $(sim-cfg-mk)
 
 .PHONY: test-cfg
 test-cfg:
+	@echo "COMPILE_OPTS" $(COMPILE_OPTS)
 	@echo "SIM_OPTS" $(SIM_OPTS)
 
 ###############################################################################
@@ -387,7 +390,7 @@ all-verilog = \
   $(shell find ../../../rtl -name '*.v' -o -name '*.sv' -o -name '*.svh') \
   $(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
 
-tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COSIM
+tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS COSIM
 -include $(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk
 tb-compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(tb-compile-var-deps))
 
@@ -405,7 +408,8 @@ $(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp: \
 	  $(verb-arg)                          \
 	  --output=$(OUT-DIR)                  \
 	  --simulator=$(SIMULATOR)             \
-	  $(cov-arg) $(wave-arg) $(cosim-arg)
+	  $(cov-arg) $(wave-arg) $(cosim-arg)  \
+	  --compile-opts="$(COMPILE_OPTS)"
 	$(call dump-vars,$(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk,comp,$(tb-compile-var-deps))
 	@touch $@
 
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
index 033c204b..a5f3158f 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml
@@ -23,6 +23,7 @@
 # gen_test        : Test name used by the instruction generator
 # asm_tests       : Path to directed, hand-coded assembly test file or directory
 # rtl_test        : RTL simulation test name
+# cmp_opts        : Compile options passed to the instruction generator
 # sim_opts        : Simulation options passed to the instruction generator
 # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
 # compare_opts    : Options for the RTL & ISS trace comparison
diff --git a/dv/uvm/core_ibex/scripts/compile-tb.py b/dv/uvm/core_ibex/scripts/compile-tb.py
index d84ea72b..ff3402fe 100755
--- a/dv/uvm/core_ibex/scripts/compile-tb.py
+++ b/dv/uvm/core_ibex/scripts/compile-tb.py
@@ -21,6 +21,7 @@ def main() -> int:
     parser.add_argument('--en_cov', action='store_true')
     parser.add_argument('--en_wave', action='store_true')
     parser.add_argument('--en_cosim', action='store_true')
+    parser.add_argument('--compile-opts', default='')
 
     args = parser.parse_args()
 
@@ -35,7 +36,11 @@ def main() -> int:
     compile_cmds, _ = get_simulator_cmd(args.simulator, enables)
 
     for pre_cmd in compile_cmds:
-        cmd = subst_vars(pre_cmd, {'out': output_dir})
+        cmd = subst_vars(pre_cmd,
+                         {
+                             'out': output_dir,
+                             'cmp_opts': args.compile_opts
+                         })
         retcode = run_one(args.verbose, ['sh', '-c', cmd],
                           discard_stdstreams=True)
         if retcode:
diff --git a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index fc6a1189..f63e5fe1 100644
--- a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -32,7 +32,7 @@
          -debug_access+pp
          -xlrm uniq_prior_final
          -CFLAGS '--std=c99 -fno-extended-identifiers'
-         -lca -kdb <wave_opts> <cov_opts> <cosim_opts>"
+         -lca -kdb <cmp_opts> <wave_opts> <cov_opts> <cosim_opts>"
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
       -cm_tgl portsonly
@@ -81,7 +81,7 @@
               +define+UVM
               -timescale \"1 ns / 1 ps \"
               -writetoplevels <out>/top.list
-              -l <out>/compile.log"
+              -l <out>/compile.log <cmp_opts>"
   sim:
     cmd: >
       vsim -64 -c <cov_opts> -do "run -a; quit -f" +designfile -f <out>/top.list <sim_opts>  -sv_seed <seed> +access +r+w +UVM_TESTNAME=<rtl_test> +UVM_VERBOSITY=UVM_LOW +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log
@@ -116,6 +116,7 @@
     cmd:
       - "vlib <out>/work"
       - "vlog -work <out>/work
+        <cmp_opts>
         -uvmver 1.2
         +define+UVM
         -f ibex_dv.f"
@@ -159,6 +160,7 @@
               -elaborate
               -l <out>/compile.log
               -xmlibdirpath <out>
+              <cmp_opts>
               <cov_opts>
               <wave_opts>"
     cov_opts: >