diff --git a/alu.sv b/alu.sv index 7e6e45c6..83b99a08 100644 --- a/alu.sv +++ b/alu.sv @@ -39,14 +39,11 @@ module alu input logic [1:0] cmp_mode_i, input logic [1:0] vec_ext_i, - output logic [31:0] adder_lsu_o, output logic [31:0] result_o, output logic flag_o ); - assign adder_lsu_o = operand_a_i + operand_b_i; - logic [31:0] operand_a_rev; // bit reversed signal of operand_a_i // bit reverse operand_a for left shifts diff --git a/ex_stage.sv b/ex_stage.sv index 580cd570..8c893b4e 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -52,16 +52,12 @@ module ex_stage input logic [1:0] mult_signed_mode_i, input logic mult_mac_en_i, - output logic [31:0] data_addr_ex_o, - // input from ID stage input logic stall_wb_i, input logic [4:0] regfile_alu_waddr_i, input logic regfile_alu_we_i, - input logic prepost_useincr_i, - // directly passed through to WB stage, not used in EX input logic regfile_we_i, input logic [4:0] regfile_waddr_i, @@ -100,8 +96,6 @@ module ex_stage logic [31:0] alu_result; logic alu_flag; - logic [31:0] alu_adder_lsu_int; // to LS unit - logic [31:0] mult_result; @@ -119,8 +113,6 @@ module ex_stage regfile_alu_wdata_fw_o = csr_rdata_i; end - assign data_addr_ex_o = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i; - // hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter) always_comb begin : hwloop_start_mux @@ -159,8 +151,6 @@ module ex_stage .cmp_mode_i ( alu_cmp_mode_i ), .vec_ext_i ( alu_vec_ext_i ), - .adder_lsu_o ( alu_adder_lsu_int ), - .result_o ( alu_result ), .flag_o ( alu_flag ) ); diff --git a/load_store_unit.sv b/load_store_unit.sv index b02e164b..9bb28520 100644 --- a/load_store_unit.sv +++ b/load_store_unit.sv @@ -42,8 +42,10 @@ module load_store_unit output logic [31:0] data_rdata_ex_o, // requested data -> to ex stage input logic data_req_ex_i, // data request -> from ex stage - input logic [31:0] data_addr_ex_i, // data address -> from ex stage output logic data_ack_int_o, // data ack -> to controller + input logic [31:0] operand_a_ex_i, // operand a from RF for address -> from ex stage + input logic [31:0] operand_b_ex_i, // operand b from RF for address -> from ex stage + input logic addr_useincr_ex_i, // use a + b or just a for address -> from ex stage input logic data_misaligned_ex_i, // misaligned access in last ld/st -> from ID/EX pipeline output logic data_misaligned_o, // misaligned access was detected -> to controller @@ -63,6 +65,8 @@ module load_store_unit input logic ex_stall_i ); + logic [31:0] data_addr_int; + // registers for data_rdata alignment and sign extension logic [1:0] data_type_q; logic [1:0] rdata_offset_q; @@ -94,21 +98,21 @@ module load_store_unit begin // Writing a word if (misaligned_st == 1'b0) begin // non-misaligned case - case (data_addr_ex_i[1:0]) + case (data_addr_int[1:0]) 2'b00: data_be = 4'b1111; 2'b01: data_be = 4'b1110; 2'b10: data_be = 4'b1100; 2'b11: data_be = 4'b1000; - endcase; // case (data_addr_ex_i[1:0]) + endcase; // case (data_addr_int[1:0]) end else begin // misaligned case - case (data_addr_ex_i[1:0]) + case (data_addr_int[1:0]) 2'b00: data_be = 4'b0000; // this is not used, but included for completeness 2'b01: data_be = 4'b0001; 2'b10: data_be = 4'b0011; 2'b11: data_be = 4'b0111; - endcase; // case (data_addr_ex_i[1:0]) + endcase; // case (data_addr_int[1:0]) end end @@ -116,12 +120,12 @@ module load_store_unit begin // Writing a half word if (misaligned_st == 1'b0) begin // non-misaligned case - case (data_addr_ex_i[1:0]) + case (data_addr_int[1:0]) 2'b00: data_be = 4'b0011; 2'b01: data_be = 4'b0110; 2'b10: data_be = 4'b1100; 2'b11: data_be = 4'b1000; - endcase; // case (data_addr_ex_i[1:0]) + endcase; // case (data_addr_int[1:0]) end else begin // misaligned case @@ -131,12 +135,12 @@ module load_store_unit 2'b10, 2'b11: begin // Writing a byte - case (data_addr_ex_i[1:0]) + case (data_addr_int[1:0]) 2'b00: data_be = 4'b0001; 2'b01: data_be = 4'b0010; 2'b10: data_be = 4'b0100; 2'b11: data_be = 4'b1000; - endcase; // case (data_addr_ex_i[1:0]) + endcase; // case (data_addr_int[1:0]) end endcase; // case (data_type_ex_i) end @@ -144,7 +148,7 @@ module load_store_unit // prepare data to be written to the memory // we handle misaligned accesses, half word and byte accesses and // register offsets here - assign wdata_offset = data_addr_ex_i[1:0] - data_reg_offset_ex_i[1:0]; + assign wdata_offset = data_addr_int[1:0] - data_reg_offset_ex_i[1:0]; always_comb begin case (wdata_offset) @@ -168,7 +172,7 @@ module load_store_unit else if (request_entered == 1'b1) // request entered FSM begin data_type_q <= data_type_ex_i; - rdata_offset_q <= data_addr_ex_i[1:0]; + rdata_offset_q <= data_addr_int[1:0]; data_sign_ext_q <= data_sign_ext_ex_i; end end @@ -355,7 +359,7 @@ module load_store_unit begin data_req_o = 1'b0; data_we_o = 1'b0; - data_addr_o = data_addr_ex_i; + data_addr_o = data_addr_int; data_wdata_o = data_wdata; data_be_o = data_be; misaligned_st = data_misaligned_ex_i; @@ -407,7 +411,7 @@ module load_store_unit begin NS = PENDING_WO_EX_STALL; end - else + else begin NS = WAIT_GNT; end @@ -490,16 +494,20 @@ module load_store_unit case (data_type_ex_i) 2'b00: // word begin - if(data_addr_ex_i[1:0] != 2'b00) + if(data_addr_int[1:0] != 2'b00) data_misaligned_o = 1'b1; end 2'b01: // half word begin - if(data_addr_ex_i[1:0] == 2'b11) + if(data_addr_int[1:0] == 2'b11) data_misaligned_o = 1'b1; end endcase // case (data_type_ex_i) end end + + // generate address from operands + assign data_addr_int = (addr_useincr_ex_i) ? (operand_a_ex_i + operand_b_ex_i) : operand_a_ex_i; + endmodule diff --git a/riscv_core.sv b/riscv_core.sv index 996bfb2f..3e80e6de 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -462,8 +462,6 @@ module riscv_core // input from ID stage .stall_wb_i ( stall_wb ), - .prepost_useincr_i ( useincr_addr_ex ), - // From ID Stage: Regfile control signals .regfile_waddr_i ( regfile_waddr_ex ), .regfile_we_i ( regfile_we_ex ), @@ -484,8 +482,6 @@ module riscv_core .regfile_we_wb_o ( regfile_we_wb ), .regfile_rb_data_wb_o ( regfile_rb_data_wb ), - .data_addr_ex_o ( data_addr_ex ), - // To hwloop regs .hwloop_start_data_o ( hwlp_start_data_ex ), .hwloop_end_data_o ( hwlp_end_data_ex ), @@ -524,8 +520,10 @@ module riscv_core .data_rdata_ex_o ( regfile_wdata ), .data_req_ex_i ( data_req_ex ), - .data_addr_ex_i ( data_addr_ex ), .data_ack_int_o ( data_ack_int ), // ack used in controller to stall + .operand_a_ex_i ( alu_operand_a_ex ), + .operand_b_ex_i ( alu_operand_b_ex ), + .addr_useincr_ex_i ( useincr_addr_ex ), .data_misaligned_ex_i ( data_misaligned_ex ), // from ID/EX pipeline .data_misaligned_o ( data_misaligned ),