diff --git a/syn/tcl/lr_synth_flow_var_setup.tcl b/syn/tcl/lr_synth_flow_var_setup.tcl
index b665e2b4..f1ef0e7b 100644
--- a/syn/tcl/lr_synth_flow_var_setup.tcl
+++ b/syn/tcl/lr_synth_flow_var_setup.tcl
@@ -14,6 +14,9 @@ set_flow_var rpt_out "./${lr_synth_out_dir}/reports" "Report output directory"
 set_flow_bool_var flatten 1 "flatten"
 set_flow_bool_var timing_run 0 "timing run"
 set_flow_bool_var ibex_branch_target_alu 0 "Enable branch target ALU in Ibex"
+set_flow_bool_var ibex_writeback_stage 0 "Enable writeback stage in Ibex"
+set_flow_bool_var ibex_bitmanip 0 "Enable bitmanip extenion for Ibex"
+set_flow_var ibex_multiplier "fast" "Multiplier implementation for Ibex (slow/fast/single-cycle)"
 
 source $lr_synth_config_file
 
diff --git a/syn/tcl/yosys_run_synth.tcl b/syn/tcl/yosys_run_synth.tcl
index 7f2de7d2..7c63960c 100644
--- a/syn/tcl/yosys_run_synth.tcl
+++ b/syn/tcl/yosys_run_synth.tcl
@@ -20,6 +20,16 @@ if { $lr_synth_ibex_branch_target_alu } {
   yosys "chparam -set BranchTargetALU 1 ibex_core"
 }
 
+if { $lr_synth_ibex_writeback_stage } {
+  yosys "chparam -set WritebackStage 1 ibex_core"
+}
+
+if { $lr_synth_ibex_bitmanip } {
+  yosys "chparam -set RV32B 1 ibex_core"
+}
+
+yosys "chparam -set MultiplierImplementation \"$lr_synth_ibex_multiplier\" ibex_core"
+
 yosys "synth $flatten_opt -top $lr_synth_top_module"
 yosys "opt -purge"