diff --git a/debug_unit.sv b/debug_unit.sv index 89637fda..3662839f 100644 --- a/debug_unit.sv +++ b/debug_unit.sv @@ -44,11 +44,11 @@ module riscv_debug_unit output logic [31:0] dbginf_data_o, // signals to core - output logic dbg_st_en_o, // Single-step trace mode enabled + output logic dbg_step_en_o, // Single-step trace mode enabled output logic [1:0] dbg_dsr_o, // debug stop register output logic stall_core_o, - output logic flush_pipe_o, + output logic stop_req_o, input logic trap_i, output logic sp_mux_o, @@ -91,7 +91,7 @@ module riscv_debug_unit bp_fsm_ns = bp_fsm_cs; stall_core_o = 1'b0; dbginf_bp_o = 1'b0; - flush_pipe_o = 1'b0; + stop_req_o = 1'b0; case (bp_fsm_cs) Idle: @@ -104,7 +104,7 @@ module riscv_debug_unit end else if(dbginf_stall_i) begin - flush_pipe_o = 1'b1; + stop_req_o = 1'b1; bp_fsm_ns = DebugStall; end end @@ -112,7 +112,7 @@ module riscv_debug_unit // A stall from adv dbg unit was seen, flush the pipeline and wait for unstalling DebugStall: begin - flush_pipe_o = 1'b1; + stop_req_o = 1'b1; if(trap_i == 1'b1) begin @@ -137,7 +137,7 @@ module riscv_debug_unit // data to GPRs and SPRs assign regfile_wdata_o = dbginf_data_i; - assign dbg_st_en_o = dmr1_q[0]; + assign dbg_step_en_o = dmr1_q[0]; assign dbg_dsr_o = dsr_q; assign npc_o = dbginf_data_i; diff --git a/exc_controller.sv b/exc_controller.sv index 20d77b28..19638563 100644 --- a/exc_controller.sv +++ b/exc_controller.sv @@ -30,6 +30,8 @@ module riscv_exc_controller output logic req_o, input logic ack_i, + output logic trap_hit_o, + // to IF stage output logic [1:0] pc_mux_o, // selects target PC for exception output logic [4:0] vec_pc_mux_o, // selects interrupt handler for vectorized interrupts @@ -39,6 +41,7 @@ module riscv_exc_controller input logic irq_enable_i, // interrupt enable bit from CSR // from decoder + input logic trap_insn_i, // trap instruction encountered (EBREAK) input logic illegal_insn_i, // illegal instruction encountered input logic ecall_insn_i, // ecall instruction encountered input logic eret_insn_i, // eret instruction encountered @@ -48,7 +51,12 @@ module riscv_exc_controller // to CSR output logic [5:0] cause_o, - output logic save_cause_o + output logic save_cause_o, + + // from debug unit + input logic dbg_stop_req_i, + input logic dbg_step_en_i, + input logic [1:0] dbg_dsr_i ); @@ -61,11 +69,25 @@ module riscv_exc_controller integer i; - assign req_int = illegal_insn_i - | ecall_insn_i + // a trap towards the debug unit is generated when one of the + // following conditions are true: + // - ebreak instruction encountered + // - single-stepping mode enabled + // - illegal instruction exception and IIE bit is set + // - IRQ and INTE bit is set and no exception is currently running + // - Debuger requests halt + assign trap_hit_o = trap_insn_i + | dbg_stop_req_i + | dbg_step_en_i + | (illegal_insn_i & dbg_dsr_i[`DSR_IIE]) + | (irq_enable_i & (|irq_i) & dbg_dsr_i[`DSR_INTE]); + + // request for exception/interrupt + assign req_int = ecall_insn_i | lsu_load_err_i | lsu_store_err_i - | (irq_enable_i & (|irq_i)); + | (illegal_insn_i & (~dbg_dsr_i[`DSR_IIE])) + | (irq_enable_i & (|irq_i) & (~dbg_dsr_i[`DSR_INTE])); // Exception cause and ISR address selection @@ -74,7 +96,7 @@ module riscv_exc_controller cause_int = 6'b0; pc_mux_int = 'x; - if (irq_enable_i) begin + if (irq_enable_i & (~dbg_dsr_i[`DSR_INTE])) begin // pc_mux_int is a critical signal, so try to get it as soon as possible if (|irq_i) pc_mux_int = `EXC_PC_IRQ; @@ -93,7 +115,7 @@ module riscv_exc_controller pc_mux_int = `EXC_PC_ECALL; end - if (illegal_insn_i) begin + if (illegal_insn_i & (~dbg_dsr_i[`DSR_IIE])) begin cause_int = 6'b0_00010; pc_mux_int = `EXC_PC_ILLINSN; end diff --git a/id_stage.sv b/id_stage.sv index 2ec9725d..921404ef 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -141,8 +141,8 @@ module riscv_id_stage input logic lsu_store_err_i, // Debug Unit Signals - input logic dbg_flush_pipe_i, - input logic dbg_st_en_i, + input logic dbg_stop_req_i, + input logic dbg_step_en_i, input logic [1:0] dbg_dsr_i, input logic dbg_stall_i, output logic dbg_trap_o, @@ -213,7 +213,6 @@ module riscv_id_stage logic exc_req, exc_ack; // handshake logic trap_hit; - assign trap_hit = 1'b0; // TODO: Fix // Register file interface logic [4:0] regfile_addr_ra_id; @@ -734,6 +733,8 @@ module riscv_id_stage .req_o ( exc_req ), .ack_i ( exc_ack ), + .trap_hit_o ( trap_hit ), + // to IF stage .pc_mux_o ( exc_pc_mux_o ), .vec_pc_mux_o ( exc_vec_pc_mux_o ), @@ -742,6 +743,7 @@ module riscv_id_stage .irq_i ( irq_i ), .irq_enable_i ( irq_enable_i ), + .trap_insn_i ( is_decoding_o & trap_insn ), .illegal_insn_i ( is_decoding_o & illegal_insn_dec ), .ecall_insn_i ( is_decoding_o & ecall_insn_dec ), .eret_insn_i ( is_decoding_o & eret_insn_dec ), @@ -750,7 +752,12 @@ module riscv_id_stage .lsu_store_err_i ( lsu_store_err_i ), .cause_o ( exc_cause_o ), - .save_cause_o ( save_exc_cause_o ) + .save_cause_o ( save_exc_cause_o ), + + // Debug Signals + .dbg_stop_req_i ( dbg_stop_req_i ), + .dbg_step_en_i ( dbg_step_en_i ), + .dbg_dsr_i ( dbg_dsr_i ) ); diff --git a/riscv_core.sv b/riscv_core.sv index f7e8fb47..e97a930d 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -197,9 +197,9 @@ module riscv_core // Debug Unit logic dbg_stall; - logic dbg_flush_pipe; + logic dbg_stop_req; logic dbg_trap; - logic dbg_st_en; // single-step trace mode enabled + logic dbg_step_en; // single-step trace mode enabled logic [1:0] dbg_dsr; // Debug Stop Register logic dbg_reg_mux; @@ -400,8 +400,8 @@ module riscv_core .lsu_store_err_i ( lsu_store_err ), // Debug Unit Signals - .dbg_flush_pipe_i ( dbg_flush_pipe ), - .dbg_st_en_i ( dbg_st_en ), + .dbg_stop_req_i ( dbg_stop_req ), + .dbg_step_en_i ( dbg_step_en ), .dbg_dsr_i ( dbg_dsr ), .dbg_stall_i ( dbg_stall ), .dbg_trap_o ( dbg_trap ), @@ -640,11 +640,11 @@ module riscv_core .dbginf_data_o ( dbginf_data_o ), // To/From Core - .dbg_st_en_o ( dbg_st_en ), + .dbg_step_en_o ( dbg_step_en ), .dbg_dsr_o ( dbg_dsr ), .stall_core_o ( dbg_stall ), - .flush_pipe_o ( dbg_flush_pipe ), + .stop_req_o ( dbg_stop_req ), .trap_i ( dbg_trap ), // register file access