diff --git a/doc/verification.rst b/doc/verification.rst
index c011d516..aaa2a6fe 100644
--- a/doc/verification.rst
+++ b/doc/verification.rst
@@ -44,8 +44,7 @@ End-to-end RTL/ISS co-simulation flow
 
    RTL/ISS co-simulation flow chart
 
-The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here’s the list of frequently
-used commands:
+The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here is the list of frequently used commands:
 
 .. code-block:: bash
 
diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv
index c521e9bd..906a181e 100644
--- a/rtl/ibex_controller.sv
+++ b/rtl/ibex_controller.sv
@@ -527,7 +527,7 @@ module ibex_controller (
                * to be transferred back to a debugging environment. It
                * generates a breakpoint exception and performs no other
                * operation. [...] ECALL and EBREAK cause the receiving
-               * privilege mode’s epc register to be set to the address of the
+               * privilege mode's epc register to be set to the address of the
                * ECALL or EBREAK instruction itself, not the address of the
                * following instruction." [Privileged Spec v1.11, p.40]
                */
diff --git a/vendor/google_riscv-dv/src/riscv_instr_base.sv b/vendor/google_riscv-dv/src/riscv_instr_base.sv
index 183addb5..67d8ed6b 100644
--- a/vendor/google_riscv-dv/src/riscv_instr_base.sv
+++ b/vendor/google_riscv-dv/src/riscv_instr_base.sv
@@ -123,7 +123,7 @@ class riscv_instr_base extends uvm_object;
     }
   }
 
-  // Registers specified by the three-bit rs1’, rs2’, and rd’ fields of the CIW, CL, CS,
+  // Registers specified by the three-bit rs1', rs2', and rd' fields of the CIW, CL, CS,
   // and CB formats
   constraint compressed_three_bits_csr_c {
     if(format inside {CIW_FORMAT, CL_FORMAT, CS_FORMAT, CB_FORMAT}) {
@@ -168,7 +168,7 @@ class riscv_instr_base extends uvm_object;
   }
 
   constraint rvc_csr_c {
-    //  Registers specified by the three-bit rs1’, rs2’, and rd’ fields of the CIW, CL, CS,
+    //  Registers specified by the three-bit rs1', rs2', and rd' fields of the CIW, CL, CS,
     //  and CB formats
     if(format inside {CIW_FORMAT, CL_FORMAT, CS_FORMAT, CB_FORMAT}) {
       rs1 inside {[S0:A5]};