diff --git a/include/riscv_config.sv b/include/riscv_config.sv index 9d3e310f..170c72a6 100644 --- a/include/riscv_config.sv +++ b/include/riscv_config.sv @@ -99,7 +99,7 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words @@ -120,13 +120,11 @@ // will merge/fuse the ID and EX stage `define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher `define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/00_all_features_enabled.sv b/scripts/example_configs/00_all_features_enabled.sv index 05f307a7..997c888d 100644 --- a/scripts/example_configs/00_all_features_enabled.sv +++ b/scripts/example_configs/00_all_features_enabled.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/01_no_mul.sv b/scripts/example_configs/01_no_mul.sv index 0149a346..7c20504e 100644 --- a/scripts/example_configs/01_no_mul.sv +++ b/scripts/example_configs/01_no_mul.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/02_no_mul_no_vec.sv b/scripts/example_configs/02_no_mul_no_vec.sv index 6b72e105..2db43ca7 100644 --- a/scripts/example_configs/02_no_mul_no_vec.sv +++ b/scripts/example_configs/02_no_mul_no_vec.sv @@ -123,13 +123,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/03_no_mul_no_vec_no_hwlp.sv b/scripts/example_configs/03_no_mul_no_vec_no_hwlp.sv index 8e38fb8f..b2645b3b 100644 --- a/scripts/example_configs/03_no_mul_no_vec_no_hwlp.sv +++ b/scripts/example_configs/03_no_mul_no_vec_no_hwlp.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/04_no_mul_no_vec_no_hwlp_no_bit.sv b/scripts/example_configs/04_no_mul_no_vec_no_hwlp_no_bit.sv index cc0c9df0..d86fbb8d 100644 --- a/scripts/example_configs/04_no_mul_no_vec_no_hwlp_no_bit.sv +++ b/scripts/example_configs/04_no_mul_no_vec_no_hwlp_no_bit.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/05_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost.sv b/scripts/example_configs/05_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost.sv index e2c2a6c6..051c36ee 100644 --- a/scripts/example_configs/05_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost.sv +++ b/scripts/example_configs/05_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/06_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special.sv b/scripts/example_configs/06_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special.sv index 43a5b863..13c4deda 100644 --- a/scripts/example_configs/06_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special.sv +++ b/scripts/example_configs/06_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/07_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs.sv b/scripts/example_configs/07_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs.sv index 55f6e571..cac31f0d 100644 --- a/scripts/example_configs/07_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs.sv +++ b/scripts/example_configs/07_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/08_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu.sv b/scripts/example_configs/08_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu.sv index 1bfd52c8..6fd8c8a5 100644 --- a/scripts/example_configs/08_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu.sv +++ b/scripts/example_configs/08_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu.sv @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/09_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif.sv b/scripts/example_configs/09_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif.sv index 2d897668..2a918766 100644 --- a/scripts/example_configs/09_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif.sv +++ b/scripts/example_configs/09_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif.sv @@ -120,13 +120,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e.sv b/scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid.sv similarity index 98% rename from scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e.sv rename to scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid.sv index b8963c26..f7944ffe 100644 --- a/scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e.sv +++ b/scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid.sv @@ -74,10 +74,9 @@ // will enable clip, min and max operations support. //`define MATH_SPECIAL_SUPPORT - // CONFIG: JUMP_IN_ID // will enable direct jump in ID. Might increase critical path of jump target. -`define JUMP_IN_ID +//`define JUMP_IN_ID // Dependent definitions @@ -100,11 +99,11 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words -`define RV32E +//`define RV32E // CONFIG: ONLY_ALIGNED // will only allow aligned memory accesses and therefore overlapping mustn't occur @@ -120,13 +119,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_no_jumpinid.sv b/scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid_rv32e.sv similarity index 99% rename from scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_no_jumpinid.sv rename to scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid_rv32e.sv index 78b67218..ec537220 100644 --- a/scripts/example_configs/10_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_no_jumpinid.sv +++ b/scripts/example_configs/11_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_no_jumpinid_rv32e.sv @@ -74,6 +74,7 @@ // will enable clip, min and max operations support. //`define MATH_SPECIAL_SUPPORT + // CONFIG: JUMP_IN_ID // will enable direct jump in ID. Might increase critical path of jump target. //`define JUMP_IN_ID @@ -99,11 +100,11 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words -//`define RV32E +`define RV32E // CONFIG: ONLY_ALIGNED // will only allow aligned memory accesses and therefore overlapping mustn't occur diff --git a/scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e_with_splittedadder.sv b/scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_rv32e_with_splittedadder.sv similarity index 99% rename from scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e_with_splittedadder.sv rename to scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_rv32e_with_splittedadder.sv index 9708b1e6..78230fa1 100644 --- a/scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_with_smallif_rv32e_with_splittedadder.sv +++ b/scripts/example_configs/12_no_mul_no_vec_no_hwlp_no_bit_no_lsuadder_no_prepost_no_special_no_3r2wregs_with_simplealu_rv32e_with_splittedadder.sv @@ -100,7 +100,7 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words @@ -120,13 +120,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/13_rv32e_merged_pipeline.sv b/scripts/example_configs/13_rv32e_merged_pipeline.sv index c352032d..9a147b78 100644 --- a/scripts/example_configs/13_rv32e_merged_pipeline.sv +++ b/scripts/example_configs/13_rv32e_merged_pipeline.sv @@ -99,7 +99,7 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words @@ -119,13 +119,11 @@ // will merge/fuse the ID and EX stage `define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/14_rv32e_merged_pipeline_only_aligned.sv b/scripts/example_configs/14_rv32e_merged_pipeline_only_aligned.sv index 67b7d3d7..ad3da890 100644 --- a/scripts/example_configs/14_rv32e_merged_pipeline_only_aligned.sv +++ b/scripts/example_configs/14_rv32e_merged_pipeline_only_aligned.sv @@ -98,7 +98,7 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words @@ -118,13 +118,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher //`define NO_JUMP_ADDER `endif -`endif `endif `endif diff --git a/scripts/example_configs/15_rv32e_merged_pipeline_only_aligned_no_jumpadder.sv b/scripts/example_configs/15_rv32e_merged_pipeline_only_aligned_no_jumpadder.sv index 21f7c682..ab2b9099 100644 --- a/scripts/example_configs/15_rv32e_merged_pipeline_only_aligned_no_jumpadder.sv +++ b/scripts/example_configs/15_rv32e_merged_pipeline_only_aligned_no_jumpadder.sv @@ -98,7 +98,7 @@ // CONFIG: SMALL_IF // will disable large FIFO in IF stage and use a more simple one. -`define SMALL_IF +//`define SMALL_IF // CONFIG: RV32E // will reduce the register file to 16 words @@ -118,13 +118,11 @@ // will merge/fuse the ID and EX stage //`define MERGE_ID_EX -`ifdef SMALL_IF `ifdef MERGE_ID_EX // CONFIG: NO_JUMP_ADDER // will use ALU adder to calculate target and get return address from prefetcher `define NO_JUMP_ADDER `endif -`endif `endif `endif