diff --git a/controller.sv b/controller.sv
index 98d8a534..e0da70e7 100644
--- a/controller.sv
+++ b/controller.sv
@@ -96,7 +96,6 @@ module zeroriscy_controller
   output logic        halt_if_o,
   output logic        halt_id_o,
 
-  output logic        misaligned_stall_o,
   input  logic        load_stall_i,
 
   input  logic        id_ready_i,                 // ID stage is ready
diff --git a/debug_unit.sv b/debug_unit.sv
index 13ed9d76..3de33f2d 100644
--- a/debug_unit.sv
+++ b/debug_unit.sv
@@ -82,9 +82,6 @@ module zeroriscy_debug_unit
 
   input  logic        sleeping_i,
 
-  input  logic        branch_in_ex_i,
-  input  logic        branch_taken_i,
-
   output logic        jump_req_o,
   output logic [31:0] jump_addr_o
 );
diff --git a/zeroriscy_core.sv b/zeroriscy_core.sv
index d0c1b195..fba4e222 100644
--- a/zeroriscy_core.sv
+++ b/zeroriscy_core.sv
@@ -665,7 +665,6 @@ module zeroriscy_core
     // signals for PPC and NPC
     .pc_if_i           ( pc_if              ), // from IF stage
     .pc_id_i           ( pc_id              ), // from ID stage
-    .pc_branch_i       ( jump_target_ex     ),
     .data_load_event_i ( data_load_event_ex ),
     .instr_valid_id_i  ( instr_valid_id     ),
 
@@ -735,56 +734,4 @@ module zeroriscy_core
   );
 `endif
 
-`ifdef SIMCHECKER
-  logic is_interrupt;
-  assign is_interrupt = (pc_mux_id == PC_EXCEPTION) && (exc_pc_mux_id == EXC_PC_IRQ);
-
-  zeroriscy_simchecker zeroriscy_simchecker_i
-  (
-    .clk              ( clk_i                                ), // always-running clock for tracing
-    .rst_n            ( rst_ni                               ),
-
-    .fetch_enable     ( fetch_enable_i                       ),
-    .boot_addr        ( boot_addr_i                          ),
-    .core_id          ( core_id_i                            ),
-    .cluster_id       ( cluster_id_i                         ),
-
-    .instr_compressed ( if_stage_i.fetch_rdata[15:0]         ),
-    .pc_set           ( pc_set                               ),
-    .if_valid         ( if_valid                             ),
-
-    .pc               ( id_stage_i.pc_id_i                   ),
-    .instr            ( id_stage_i.instr                     ),
-    .is_compressed    ( is_compressed_id                     ),
-    .id_valid         ( id_stage_i.id_valid_o                ),
-    .is_decoding      ( id_stage_i.is_decoding_o             ),
-    .is_illegal       ( id_stage_i.illegal_insn_dec          ),
-    .is_interrupt     ( is_interrupt                         ),
-    .irq_no           ( irq_id_i                             ),
-    .pipe_flush       ( id_stage_i.controller_i.pipe_flush_i ),
-
-    .ex_valid         (                              ),
-    .ex_reg_addr      ( id_stage_i.registers_i.waddr_b_i     ),
-    .ex_reg_we        ( id_stage_i.registers_i.we_a_i        ),
-    .ex_reg_wdata     ( id_stage_i.registers_i.wdata_b_i     ),
-
-    .ex_data_addr     ( data_addr_o                          ),
-    .ex_data_req      ( data_req_o                           ),
-    .ex_data_gnt      ( data_gnt_i                           ),
-    .ex_data_we       ( data_we_o                            ),
-    .ex_data_wdata    ( data_wdata_o                         ),
-
-    .wb_bypass        ( ex_block_i.branch_in_ex_i            ),
-    .lsu_misaligned   ( data_misaligned                      ),
-
-    .wb_valid         ( wb_valid                             ),
-    .wb_reg_addr      ( id_stage_i.registers_i.waddr_a_i     ),
-    .wb_reg_we        ( id_stage_i.registers_i.we_a_i        ),
-    .wb_reg_wdata     ( id_stage_i.registers_i.wdata_a_i     ),
-
-    .wb_data_rvalid   ( data_rvalid_i                        ),
-    .wb_data_rdata    ( data_rdata_i                         )
-  );
-`endif
-
 endmodule