diff --git a/controller.sv b/controller.sv
index 33215e10..b7a6f64e 100644
--- a/controller.sv
+++ b/controller.sv
@@ -987,6 +987,16 @@ module controller
       end
     endcase
 
+    // synopsys translate_off
+    // print warning in case of decoding errors
+    // note: this is done intentionally before checking RVC decoding, to
+    // suppress wrong (and annoying) messages during simulation
+    if (illegal_insn_int) begin
+      $warning("Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
+      //prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
+    end
+    // synopsys translate_on
+
     // make sure invalid compressed instruction causes an exception
     if (illegal_c_insn_i) begin
       illegal_insn_int = 1'b1;
@@ -1093,12 +1103,6 @@ module controller
         // handle illegal instructions
         if (illegal_insn_int) begin
           illegal_insn_o = 1'b1;
-
-          // synopsys translate_off
-          $display("%t: Illegal instruction (core %0d) at PC 0x%h", $time, riscv_core.core_id_i,
-                   id_stage.current_pc_id_i);
-          //prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
-          // synopsys translate_on
         end
 
         // the pipeline is flushed and we are requested to go to sleep