diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv
index 0cd1c855..c3d3f46d 100644
--- a/rtl/ibex_if_stage.sv
+++ b/rtl/ibex_if_stage.sv
@@ -109,6 +109,10 @@ module ibex_if_stage #(
   logic        [5:0] irq_id;
   logic              unused_irq_bit;
 
+  logic        [7:0] unused_boot_addr;
+
+  assign unused_boot_addr = boot_addr_i[7:0];
+
   // extract interrupt ID from exception cause
   assign irq_id         = {exc_cause};
   assign unused_irq_bit = irq_id[5];   // MSB distinguishes interrupts from exceptions
diff --git a/rtl/ibex_register_file_ff.sv b/rtl/ibex_register_file_ff.sv
index 86e7a082..07907ec7 100644
--- a/rtl/ibex_register_file_ff.sv
+++ b/rtl/ibex_register_file_ff.sv
@@ -61,7 +61,7 @@ module ibex_register_file #(
   logic [NUM_WORDS-1:1]                we_a_dec;
 
   always_comb begin : we_a_decoder
-    for (int i = 1; i < NUM_WORDS; i++) begin
+    for (int unsigned i = 1; i < NUM_WORDS; i++) begin
       we_a_dec[i] = (waddr_a_i == 5'(i)) ?  we_a_i : 1'b0;
     end
   end