diff --git a/alu.sv b/alu.sv
index 45cc0730..7cfa3397 100644
--- a/alu.sv
+++ b/alu.sv
@@ -472,7 +472,6 @@ module riscv_alu
   assign clip_is_lower_neg = adder_result[31];
   assign clip_is_lower_u   = (operator_i == ALU_CLIPU) && operand_a_i[31];
 
-  //assign clip_result       = clip_is_lower_u ? '0 : (clip_is_lower_neg ? operand_b_neg : result_minmax);
   assign clip_result       = is_greater ? result_minmax: (clip_is_lower_u ? '0 : (clip_is_lower_neg ? operand_b_neg : result_minmax));
   //////////////////////////////////////////////////
   //  ____  _   _ _   _ _____ _____ _     _____   //
diff --git a/decoder.sv b/decoder.sv
index d4923764..7b7eede0 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -141,9 +141,6 @@ module riscv_decoder
 
   logic [1:0] csr_op;
 
-  logic davide;
-
-
   /////////////////////////////////////////////
   //   ____                     _            //
   //  |  _ \  ___  ___ ___   __| | ___ _ __  //
@@ -227,10 +224,8 @@ module riscv_decoder
     bmask_b_mux_o               = BMASK_B_ZERO;
     alu_bmask_a_mux_sel_o       = BMASK_A_IMM;
     alu_bmask_b_mux_sel_o       = BMASK_B_IMM;
-    davide = '0;
     `endif // BIT_SUPPORT
 
-
     unique case (instr_rdata_i[6:0])
 
       //////////////////////////////////////
@@ -548,7 +543,6 @@ module riscv_decoder
 
             3'b100: begin
               alu_operator_o = ALU_BSET;
-              davide = 1'b1;
               if (~instr_rdata_i[30]) begin
                 //register variant
                 regb_used_o            = 1'b1;