diff --git a/doc/verification.rst b/doc/verification.rst
index aaa2a6fe..3998e3bb 100644
--- a/doc/verification.rst
+++ b/doc/verification.rst
@@ -30,11 +30,13 @@ Please note that this work is still working in progress.
 Getting Started
 ---------------
 
-Prerequisites
-~~~~~~~~~~~~~
+Prerequisites & Environment Setup
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  VCS RTL simulator (need to support UVM 1.2)
--  `Setup the RISC-V instruction generator and ISS sim environment <https://github.com/google/riscv-dv#getting-started>`_
+- VCS RTL simulator (needed to support UVM 1.2)
+- RISCV-DV Prerequisites - https://github.com/google/riscv-dv#prerequisites
+- GCC setup - https://github.com/google/riscv-dv#compile-generated-programs-with-gcc
+- ISS setup - https://github.com/google/riscv-dv#run-iss-instruction-set-simulator-simulation - note that commit log must be enabled in spike by passing ``--enable-commitlog`` to the configure script.
 
 End-to-end RTL/ISS co-simulation flow
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~