diff --git a/controller.sv b/controller.sv index a38ffe31..db5686b6 100644 --- a/controller.sv +++ b/controller.sv @@ -59,15 +59,15 @@ module riscv_controller output logic instr_req_o, // Start fetching instructions // to prefetcher - output logic pc_set_o, // jump to address set by pc_mux_sel - output logic [2:0] pc_mux_sel_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...) + output logic pc_set_o, // jump to address set by pc_mux + output logic [2:0] pc_mux_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...) // LSU input logic data_req_ex_i, // data memory access is currently performed in EX stage input logic data_misaligned_i, // hwloop signals - input logic hwloop_jump_i, // modify pc_mux_sel to select the hwloop addr + input logic hwloop_jump_i, // modify pc_mux to select the hwloop addr // jump/branch signals input logic branch_taken_ex_i, // branch taken signal from EX ALU @@ -173,7 +173,7 @@ module riscv_controller save_pc_if_o = 1'b0; save_pc_id_o = 1'b0; - pc_mux_sel_o = `PC_BOOT; + pc_mux_o = `PC_BOOT; pc_set_o = 1'b0; ctrl_fsm_ns = ctrl_fsm_cs; @@ -200,7 +200,7 @@ module riscv_controller BOOT_SET: begin instr_req_o = 1'b1; - pc_mux_sel_o = `PC_BOOT; + pc_mux_o = `PC_BOOT; pc_set_o = 1'b1; ctrl_fsm_ns = FIRST_FETCH; @@ -231,13 +231,13 @@ module riscv_controller // hwloop detected, jump to start address! // Attention: This has to be done in the DECODE and the FIRST_FETCH states if (hwloop_jump_i == 1'b1) begin - pc_mux_sel_o = `PC_HWLOOP; + pc_mux_o = `PC_HWLOOP; pc_set_o = 1'b1; end // handle exceptions if (exc_req_i) begin - pc_mux_sel_o = `PC_EXCEPTION; + pc_mux_o = `PC_EXCEPTION; pc_set_o = 1'b1; exc_ack_o = 1'b1; @@ -268,7 +268,7 @@ module riscv_controller // we don't need to worry about conditional branches here as they // will be evaluated in the EX stage if (jump_in_dec_i == `BRANCH_JALR || jump_in_dec_i == `BRANCH_JAL) begin - pc_mux_sel_o = `PC_JUMP; + pc_mux_o = `PC_JUMP; // if there is a jr stall, wait for it to be gone if (~jr_stall_o) @@ -281,13 +281,13 @@ module riscv_controller // handle hwloops if (hwloop_jump_i) begin - pc_mux_sel_o = `PC_HWLOOP; - pc_set_o = 1'b1; + pc_mux_o = `PC_HWLOOP; + pc_set_o = 1'b1; end if (eret_insn_i) begin - pc_mux_sel_o = `PC_ERET; - pc_set_o = 1'b1; + pc_mux_o = `PC_ERET; + pc_set_o = 1'b1; end // handle WFI instruction, flush pipeline and (potentially) go to @@ -309,7 +309,7 @@ module riscv_controller begin ctrl_fsm_ns = JUMP_EXC; end else begin - pc_mux_sel_o = `PC_EXCEPTION; + pc_mux_o = `PC_EXCEPTION; pc_set_o = 1'b1; exc_ack_o = 1'b1; @@ -347,7 +347,7 @@ module riscv_controller // handle conditional branches if (branch_taken_ex_i) begin // there is a branch in the EX stage that is taken - pc_mux_sel_o = `PC_BRANCH; + pc_mux_o = `PC_BRANCH; pc_set_o = 1'b1; is_decoding_o = 1'b0; // we are not decoding the current instruction in the ID stage @@ -369,8 +369,8 @@ module riscv_controller if (branch_taken_ex_i) begin // there is a branch in the EX stage that is taken - pc_mux_sel_o = `PC_BRANCH; - pc_set_o = 1'b1; + pc_mux_o = `PC_BRANCH; + pc_set_o = 1'b1; end ctrl_fsm_ns = DBG_SIGNAL; @@ -393,7 +393,7 @@ module riscv_controller halt_if_o = 1'b1; if(dbg_set_npc_i == 1'b1) begin - pc_mux_sel_o = `PC_DBG_NPC; + pc_mux_o = `PC_DBG_NPC; pc_set_o = 1'b1; ctrl_fsm_ns = DBG_WAIT; end @@ -436,7 +436,7 @@ module riscv_controller // we can just save the IF PC, since it propagated through the // prefetcher save_pc_if_o = 1'b1; - pc_mux_sel_o = `PC_EXCEPTION; + pc_mux_o = `PC_EXCEPTION; pc_set_o = 1'b1; exc_ack_o = 1'b1; diff --git a/id_stage.sv b/id_stage.sv index 2944fc68..2ec9725d 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -62,7 +62,7 @@ module riscv_id_stage // IF and ID stage signals output logic clear_instr_valid_o, output logic pc_set_o, - output logic [2:0] pc_mux_sel_o, + output logic [2:0] pc_mux_o, output logic [1:0] exc_pc_mux_o, output logic [4:0] exc_vec_pc_mux_o, @@ -654,7 +654,7 @@ module riscv_id_stage // to prefetcher .pc_set_o ( pc_set_o ), - .pc_mux_sel_o ( pc_mux_sel_o ), + .pc_mux_o ( pc_mux_o ), // LSU .data_req_ex_i ( data_req_ex_o ), diff --git a/if_stage.sv b/if_stage.sv index 7d13f381..5a18ea33 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -66,7 +66,7 @@ module riscv_if_stage input logic clear_instr_valid_i, // clear instruction valid bit in IF/ID pipe input logic pc_set_i, // set the program counter to a new value input logic [31:0] exception_pc_reg_i, // address used to restore PC when the interrupt/exception is served - input logic [2:0] pc_mux_sel_i, // sel for pc multiplexer + input logic [2:0] pc_mux_i, // sel for pc multiplexer input logic [1:0] exc_pc_mux_i, // selects ISR address input logic [4:0] exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines @@ -125,8 +125,8 @@ module riscv_if_stage always_comb begin // default values for regular aligned access - instr_rdata_int = fetch_rdata; current_pc_if_o = {fetch_addr[31:2], 2'b00}; + instr_rdata_int = fetch_rdata; if (unaligned) begin current_pc_if_o = {fetch_addr[31:2], 2'b10}; @@ -143,20 +143,28 @@ module riscv_if_stage // exception PC selection mux always_comb begin : EXC_PC_MUX + exc_pc = 'x; unique case (exc_pc_mux_i) `EXC_PC_ILLINSN: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ILLINSN }; `EXC_PC_ECALL: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ECALL }; `EXC_PC_LOAD: exc_pc = { boot_addr_i[31:8], `EXC_OFF_LSUERR }; `EXC_PC_IRQ: exc_pc = { boot_addr_i[31:8], 1'b0, exc_vec_pc_mux_i[4:0], 2'b0 }; // TODO: Add case for EXC_PC_STORE as soon as it differs from load - default: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ILLINSN }; + + default: begin + // synopsys translate_off + $display("%t: Illegal exc pc_mux value (%0d)!", $time, exc_pc_mux_i); + // synopsys translate_on + end endcase end // fetch address selection always_comb begin - unique case (pc_mux_sel_i) + fetch_addr_n = 'x; + + unique case (pc_mux_i) `PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], `EXC_OFF_RST}; `PC_JUMP: fetch_addr_n = {jump_target_id_i[31:2], 2'b0}; `PC_BRANCH: fetch_addr_n = {jump_target_ex_i[31:2], 2'b0}; @@ -164,11 +172,10 @@ module riscv_if_stage `PC_ERET: fetch_addr_n = exception_pc_reg_i; // PC is restored when returning from IRQ/exception `PC_HWLOOP: fetch_addr_n = hwloop_target_i; // PC is taken from hwloop start addr `PC_DBG_NPC: fetch_addr_n = dbg_npc_i; // PC is taken from debug unit - default: - begin - fetch_addr_n = 'X; + + default: begin // synopsys translate_off - $display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_sel_i); + $display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_i); // synopsys translate_on end endcase @@ -178,7 +185,7 @@ module riscv_if_stage begin unaligned_jump = 1'b0; - case (pc_mux_sel_i) + case (pc_mux_i) `PC_JUMP: unaligned_jump = jump_target_id_i[1]; `PC_BRANCH: unaligned_jump = jump_target_ex_i[1]; `PC_ERET: unaligned_jump = exception_pc_reg_i[1]; diff --git a/riscv_core.sv b/riscv_core.sv index c7f995cd..f7e8fb47 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -94,7 +94,7 @@ module riscv_core logic clear_instr_valid; logic pc_set; - logic [2:0] pc_mux_sel_id; // Mux selector for next PC + logic [2:0] pc_mux_id; // Mux selector for next PC logic [1:0] exc_pc_mux_id; // Mux selector for exception PC logic [4:0] exc_vec_pc_mux_id; // Mux selector for vectorized IR lines @@ -266,7 +266,7 @@ module riscv_core .clear_instr_valid_i ( clear_instr_valid ), .pc_set_i ( pc_set ), .exception_pc_reg_i ( epcr ), // exception return address - .pc_mux_sel_i ( pc_mux_sel_id ), // sel for pc multiplexer + .pc_mux_i ( pc_mux_id ), // sel for pc multiplexer .exc_pc_mux_i ( exc_pc_mux_id ), .exc_vec_pc_mux_i ( exc_vec_pc_mux_id ), @@ -326,7 +326,7 @@ module riscv_core // IF and ID control signals .clear_instr_valid_o ( clear_instr_valid ), .pc_set_o ( pc_set ), - .pc_mux_sel_o ( pc_mux_sel_id ), + .pc_mux_o ( pc_mux_id ), .exc_pc_mux_o ( exc_pc_mux_id ), .exc_vec_pc_mux_o ( exc_vec_pc_mux_id ),