diff --git a/hwloop_controller.sv b/hwloop_controller.sv
index 254469c3..63f28076 100644
--- a/hwloop_controller.sv
+++ b/hwloop_controller.sv
@@ -31,60 +31,61 @@
 `include "defines.sv"
 
 module hwloop_controller
-  (
+(
+  // from id stage
+  input  logic                           enable_i,
+  input  logic [31:0]                    current_pc_i,
 
-   // from id stage
-   input  logic                           enable_i,
-   input  logic [31:0]                    current_pc_i,
+  // from hwloop_regs
+  input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i,
+  input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_i,
+  input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_i,
 
-   // from hwloop_regs
-   input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i,
-   input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_i,
-   input  logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_i,
+  // to hwloop_regs
+  output logic [`HWLOOP_REGS-1:0]        hwloop_dec_cnt_o,
 
-   // to hwloop_regs
-   output logic [`HWLOOP_REGS-1:0]        hwloop_dec_cnt_o,
-
-   // to id stage
-   output logic                           hwloop_jump_o,
-   output logic [31:0]                    hwloop_targ_addr_o
-   );
+  // to id stage
+  output logic                           hwloop_jump_o,
+  output logic [31:0]                    hwloop_targ_addr_o
+);
 
 
-   logic [`HWLOOP_REGS-1:0] pc_is_end_addr;
+  logic [`HWLOOP_REGS-1:0] pc_is_end_addr;
+
 
    // generate comparators. check for end address and the loop counter
-   genvar i;
-   for (i = 0; i < `HWLOOP_REGS; i++) begin
-     assign pc_is_end_addr[i] = ((current_pc_i == hwloop_end_addr_i[i]) & (enable_i) & (hwloop_counter_i[i] > 32'b1)) ? 1'b1 : 1'b0;
-   end
+  genvar i;
+  for (i = 0; i < `HWLOOP_REGS; i++) begin
+    assign pc_is_end_addr[i] = ((current_pc_i == hwloop_end_addr_i[i]) & (enable_i) & (hwloop_counter_i[i] > 32'b1)) ? 1'b1 : 1'b0;
+  end
 
-   // output signal for ID stage
-   assign hwloop_jump_o = |pc_is_end_addr;
+  // output signal for ID stage
+  assign hwloop_jump_o = |pc_is_end_addr;
 
-   // select corresponding start address and decrement counter. give highest priority to register 0
-   always_comb begin
-      hwloop_targ_addr_o = 32'b0;
-      hwloop_dec_cnt_o = `HWLOOP_REGS'b0;
 
-      if (pc_is_end_addr[0]) begin
-        hwloop_targ_addr_o = hwloop_start_addr_i[0];
-        hwloop_dec_cnt_o[0] = 1'b1;
-      end
-      else if (pc_is_end_addr[1]) begin
-        hwloop_targ_addr_o = hwloop_start_addr_i[1];
-        hwloop_dec_cnt_o[1] = 1'b1;
-      end
+  // select corresponding start address and decrement counter. give highest priority to register 0
+  always_comb begin
+    hwloop_targ_addr_o = 32'b0;
+    hwloop_dec_cnt_o = `HWLOOP_REGS'b0;
+
+    if (pc_is_end_addr[0]) begin
+      hwloop_targ_addr_o = hwloop_start_addr_i[0];
+      hwloop_dec_cnt_o[0] = 1'b1;
+    end
+    else if (pc_is_end_addr[1]) begin
+      hwloop_targ_addr_o = hwloop_start_addr_i[1];
+      hwloop_dec_cnt_o[1] = 1'b1;
+    end
 /* -----\/----- EXCLUDED -----\/-----
-      else if (pc_is_end_addr[2]) begin
-        hwloop_targ_addr_o = hwloop_start_addr_i[2];
-        hwloop_dec_cnt_o[2] = 1'b1;
-      end
-      else if (pc_is_end_addr[3]) begin
-        hwloop_targ_addr_o = hwloop_start_addr_i[3];
-        hwloop_dec_cnt_o[3] = 1'b1;
-      end
+    else if (pc_is_end_addr[2]) begin
+      hwloop_targ_addr_o = hwloop_start_addr_i[2];
+      hwloop_dec_cnt_o[2] = 1'b1;
+    end
+    else if (pc_is_end_addr[3]) begin
+      hwloop_targ_addr_o = hwloop_start_addr_i[3];
+      hwloop_dec_cnt_o[3] = 1'b1;
+    end
  -----/\----- EXCLUDED -----/\----- */
-   end
+  end
 
 endmodule
diff --git a/hwloop_regs.sv b/hwloop_regs.sv
index 7ef9b92f..264a7e56 100644
--- a/hwloop_regs.sv
+++ b/hwloop_regs.sv
@@ -31,28 +31,28 @@
 `include "defines.sv"
 
 module hwloop_regs
-  (
-    input  logic        clk,
-    input  logic        rst_n,
+(
+  input  logic        clk,
+  input  logic        rst_n,
 
-    // from ex stage
-    input  logic [31:0] hwloop_start_data_i,
-    input  logic [31:0] hwloop_end_data_i,
-    input  logic [31:0] hwloop_cnt_data_i,
-    input  logic  [2:0] hwloop_we_i,
-    input  logic  [1:0] hwloop_regid_i,         // selects the register set
+  // from ex stage
+  input  logic [31:0] hwloop_start_data_i,
+  input  logic [31:0] hwloop_end_data_i,
+  input  logic [31:0] hwloop_cnt_data_i,
+  input  logic  [2:0] hwloop_we_i,
+  input  logic  [1:0] hwloop_regid_i,         // selects the register set
 
-    // from controller
-    input  logic        stall_id_i,
+  // from controller
+  input  logic        stall_id_i,
 
-    // from hwloop controller
-    input  logic [`HWLOOP_REGS-1:0]        hwloop_dec_cnt_i,
+  // from hwloop controller
+  input  logic [`HWLOOP_REGS-1:0]        hwloop_dec_cnt_i,
 
-    // to hwloop controller
-    output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_o,
-    output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_o,
-    output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_o
-  );
+  // to hwloop controller
+  output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_o,
+  output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_o,
+  output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_o
+);
 
 
   logic [`HWLOOP_REGS-1:0] [31:0]        hwloop_start_regs_q;