diff --git a/rtl/ibex_register_file_latch.sv b/rtl/ibex_register_file_latch.sv
index 7b3c781a..a5ec5503 100644
--- a/rtl/ibex_register_file_latch.sv
+++ b/rtl/ibex_register_file_latch.sv
@@ -46,7 +46,7 @@ module ibex_register_file #(
   logic [NUM_WORDS-1:1] mem_clocks;
   logic [DataWidth-1:0] wdata_a_q;
 
-  // Write port W1
+  // internal addresses
   logic [ADDR_WIDTH-1:0] raddr_a_int, raddr_b_int, waddr_a_int;
 
   assign raddr_a_int = raddr_a_i[ADDR_WIDTH-1:0];
@@ -55,24 +55,25 @@ module ibex_register_file #(
 
   logic clk_int;
 
-  //////////////////////////////////////
-  // READ: Read address decoder (RAD) //
-  //////////////////////////////////////
+  //////////
+  // READ //
+  //////////
   assign rdata_a_o = mem[raddr_a_int];
   assign rdata_b_o = mem[raddr_b_int];
 
-  ///////////////////////////////
-  // WRITE: SAMPLE INPUT DATA //
-  ///////////////////////////////
-
+  ///////////
+  // WRITE //
+  ///////////
+  // Global clock gating
   prim_clock_gating cg_we_global (
-      .clk_i     ( clk_i           ),
-      .en_i      ( we_a_i          ),
-      .test_en_i ( test_en_i       ),
-      .clk_o     ( clk_int         )
+      .clk_i     ( clk_i     ),
+      .en_i      ( we_a_i    ),
+      .test_en_i ( test_en_i ),
+      .clk_o     ( clk_int   )
   );
 
-  // use clk_int here, since otherwise we don't want to write anything anyway
+  // Sample input data
+  // Use clk_int here, since otherwise we don't want to write anything anyway.
   always_ff @(posedge clk_int or negedge rst_ni) begin : sample_wdata
     if (!rst_ni) begin
       wdata_a_q   <= '0;
@@ -83,9 +84,7 @@ module ibex_register_file #(
     end
   end
 
-  ///////////////////////////////////////////////////////////////
-  // WRITE: Write Address Decoder (WAD), combinatorial process //
-  ///////////////////////////////////////////////////////////////
+  // Write address decoding
   always_comb begin : wad
     for (int i = 1; i < NUM_WORDS; i++) begin : wad_word_iter
       if (we_a_i && (waddr_a_int == i)) begin
@@ -96,9 +95,7 @@ module ibex_register_file #(
     end
   end
 
-  //////////////////////////////////////////////////////////////////////////
-  // WRITE: Clock gating (if integrated clock-gating cells are available) //
-  //////////////////////////////////////////////////////////////////////////
+  // Individual clock gating (if integrated clock-gating cells are available)
   for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
     prim_clock_gating cg_i (
         .clk_i     ( clk_int           ),
@@ -108,19 +105,11 @@ module ibex_register_file #(
     );
   end
 
-  ////////////////////////////
-  // WRITE: Write operation //
-  ////////////////////////////
-  // Generate M = WORDS sequential processes, each of which describes one
-  // word of the memory. The processes are synchronized with the clocks
-  // ClocksxC(i), i = 0, 1, ..., M-1
-  // Use active low, i.e. transparent on low latches as storage elements
-  // Data is sampled on rising clock edge
-
+  // Actual write operation:
+  // Generate the sequential process for the NUM_WORDS words of the memory.
+  // The process is synchronized with the clocks mem_clocks[k], k = 1, ..., NUM_WORDS-1.
   always_latch begin : latch_wdata
-    // Note: The assignment has to be done inside this process or Modelsim complains about it
     mem[0] = '0;
-
     for (int k = 1; k < NUM_WORDS; k++) begin : latch_wdata_word_iter
       if (mem_clocks[k]) begin
         mem[k] = wdata_a_q;