From 6ee9f3fe924d81564202e94deb63b8c394e7a038 Mon Sep 17 00:00:00 2001 From: Andreas Traber Date: Thu, 31 Mar 2016 10:32:19 +0200 Subject: [PATCH] Fix wrong ordering of instructions in tracer in some cases --- riscv_tracer.sv | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/riscv_tracer.sv b/riscv_tracer.sv index 6482e646..f9fa173d 100644 --- a/riscv_tracer.sv +++ b/riscv_tracer.sv @@ -546,8 +546,8 @@ module riscv_tracer endfunction endclass - mailbox instr_ex = new (2); - mailbox instr_wb = new (2); + mailbox #(instr_trace_t) instr_ex = new (); + mailbox #(instr_trace_t) instr_wb = new (); // cycle counter always_ff @(posedge clk, negedge rst_n) @@ -612,10 +612,7 @@ module riscv_tracer end end while (!ex_valid && !wb_bypass); // ex branches bypass the WB stage - if (wb_bypass) - trace.printInstrTrace(); - else - instr_wb.put(trace); + instr_wb.put(trace); end end