diff --git a/rtl/ibex_alu.sv b/rtl/ibex_alu.sv
index f2ffb4ba..7f4af6c1 100644
--- a/rtl/ibex_alu.sv
+++ b/rtl/ibex_alu.sv
@@ -117,7 +117,9 @@ module ibex_alu (
 
   assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a};
 
-  assign shift_right_result = $unsigned($signed(shift_op_a_32) >>> shift_amt[4:0]);
+  logic signed [32:0] shift_right_result_signed;
+  assign shift_right_result_signed = $signed(shift_op_a_32) >>> shift_amt[4:0];
+  assign shift_right_result        = shift_right_result_signed[31:0];
 
   // bit reverse the shift_right_result for left shifts
   for (genvar j = 0; j < 32; j++) begin : gen_resrevloop
diff --git a/rtl/ibex_multdiv_fast.sv b/rtl/ibex_multdiv_fast.sv
index 7f81af42..b37ca209 100644
--- a/rtl/ibex_multdiv_fast.sv
+++ b/rtl/ibex_multdiv_fast.sv
@@ -56,7 +56,8 @@ module ibex_multdiv_fast (
   } div_fsm_e;
   div_fsm_e divcurr_state_q, divcurr_state_n;
 
-  logic [34:0] mac_res_ext;
+  logic signed [34:0] mac_res_ext;
+
   logic [33:0] mac_res_q, mac_res_n, mac_res, op_reminder_n;
   logic [15:0] mult_op_a;
   logic [15:0] mult_op_b;