From 71a1fc6af4beb330a222d95584f3038cad562e96 Mon Sep 17 00:00:00 2001
From: Pascal Nasahl <nasahlpa@lowrisc.org>
Date: Mon, 9 Jun 2025 11:29:20 +0200
Subject: [PATCH] [syn] Add keep_hierarchy constraints to prim_generic

Some FI countermeasures in Ibex use redundancy to detect fault attacks
(e.g., the onehot encoding & checker in the RF). As synthesis tools
are great in detecting redundant logic and reducing it, this commit
puts a keep_hierarchy synthesis constraint on prim_generic* modules.
This is exactely the purpose of the prim_generic_buf, prim_generic_flop,
and prim_generic_and2 modules - having synthesis barriers to avoid
optimizations.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
---
 syn/tcl/yosys_run_synth.tcl | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/syn/tcl/yosys_run_synth.tcl b/syn/tcl/yosys_run_synth.tcl
index 24221e59..01de2d64 100644
--- a/syn/tcl/yosys_run_synth.tcl
+++ b/syn/tcl/yosys_run_synth.tcl
@@ -24,16 +24,23 @@ if { $lr_synth_ibex_writeback_stage } {
   yosys "chparam -set WritebackStage 1 $lr_synth_top_module"
 }
 
-if { $lr_synth_ibex_secure_ibex } {
-  yosys "chparam -set SecureIbex 1 $lr_synth_top_module"
-}
-
 yosys "chparam -set RV32B $lr_synth_ibex_bitmanip $lr_synth_top_module"
 
 yosys "chparam -set RV32M $lr_synth_ibex_multiplier $lr_synth_top_module"
 
 yosys "chparam -set RegFile $lr_synth_ibex_regfile $lr_synth_top_module"
 
+if { $lr_synth_ibex_secure_ibex } {
+  yosys "chparam -set SecureIbex 1 $lr_synth_top_module"
+  # Place keep_hierarchy contraints on relevant modules to prevent aggressive
+  # synthesis optimzations across the boundaries of these modules.
+  yosys "hierarchy -check -top $lr_synth_top_module"
+  yosys "setattr -mod -set keep_hierarchy 1 *prim_generic_and2*"
+  yosys "setattr -mod -set keep_hierarchy 1 *prim_generic_buf*"
+  yosys "setattr -mod -set keep_hierarchy 1 *prim_generic_clock_mux2*"
+  yosys "setattr -mod -set keep_hierarchy 1 *prim_generic_flop*"
+}
+
 yosys "synth $flatten_opt -top $lr_synth_top_module"
 yosys "opt -purge"
 
@@ -53,6 +60,20 @@ if { $lr_synth_timing_run } {
   yosys "abc -liberty $lr_synth_cell_library_path"
 }
 
+if { $lr_synth_ibex_secure_ibex } {
+  # Remove keep_hierarchy constraints before the final flattening step.
+  # We're done optimizing.
+  yosys "setattr -mod -set keep_hierarchy 0 *prim_generic_and2*"
+  yosys "setattr -mod -set keep_hierarchy 0 *prim_generic_buf*"
+  yosys "setattr -mod -set keep_hierarchy 0 *prim_generic_clock_mux2*"
+  yosys "setattr -mod -set keep_hierarchy 0 *prim_generic_flop*"
+}
+
+# Final flattening.
+if { $lr_synth_flatten } {
+  yosys "flatten"
+}
+
 yosys "clean"
 yosys "write_verilog $lr_synth_netlist_out"