From 72e9bcd488cd896549cdef3e8ffcc6bf92b51ed5 Mon Sep 17 00:00:00 2001 From: Saad Khalid Date: Thu, 26 Jan 2023 21:00:38 +0000 Subject: [PATCH] vendored riscv test env for common macro files --- .../access_pmp_overlap/access_pmp_overlap.S | 10 + .../directed_tests/directed_testlist.yaml | 10 + dv/uvm/core_ibex/directed_tests/ibex_macros.h | 1 + dv/uvm/core_ibex/directed_tests/test_macros.h | 754 -------- vendor/patches/riscv_test_env/changes.patch | 89 + vendor/riscv-test-env/LICENSE | 24 + .../riscv-test-env}/encoding.h | 1714 ++++++++--------- vendor/riscv-test-env/p/link.ld | 17 + .../riscv-test-env/p}/riscv_test.h | 1 + vendor/riscv-test-env/pm/link.ld | 17 + vendor/riscv-test-env/pm/riscv_test.h | 11 + vendor/riscv-test-env/pt/link.ld | 17 + vendor/riscv-test-env/pt/riscv_test.h | 69 + vendor/riscv-test-env/v/entry.S | 162 ++ vendor/riscv-test-env/v/link.ld | 17 + vendor/riscv-test-env/v/riscv_test.h | 80 + vendor/riscv-test-env/v/string.c | 114 ++ vendor/riscv-test-env/v/vm.c | 300 +++ vendor/riscv_test_env.lock.hjson | 15 + vendor/riscv_test_env.vendor.hjson | 12 + 20 files changed, 1801 insertions(+), 1633 deletions(-) delete mode 100644 dv/uvm/core_ibex/directed_tests/test_macros.h create mode 100644 vendor/patches/riscv_test_env/changes.patch create mode 100644 vendor/riscv-test-env/LICENSE rename {dv/uvm/core_ibex/directed_tests => vendor/riscv-test-env}/encoding.h (73%) create mode 100644 vendor/riscv-test-env/p/link.ld rename {dv/uvm/core_ibex/directed_tests => vendor/riscv-test-env/p}/riscv_test.h (99%) create mode 100644 vendor/riscv-test-env/pm/link.ld create mode 100644 vendor/riscv-test-env/pm/riscv_test.h create mode 100644 vendor/riscv-test-env/pt/link.ld create mode 100644 vendor/riscv-test-env/pt/riscv_test.h create mode 100644 vendor/riscv-test-env/v/entry.S create mode 100644 vendor/riscv-test-env/v/link.ld create mode 100644 vendor/riscv-test-env/v/riscv_test.h create mode 100644 vendor/riscv-test-env/v/string.c create mode 100644 vendor/riscv-test-env/v/vm.c create mode 100644 vendor/riscv_test_env.lock.hjson create mode 100644 vendor/riscv_test_env.vendor.hjson diff --git a/dv/uvm/core_ibex/directed_tests/access_pmp_overlap/access_pmp_overlap.S b/dv/uvm/core_ibex/directed_tests/access_pmp_overlap/access_pmp_overlap.S index 54583dc8..79d8fedc 100644 --- a/dv/uvm/core_ibex/directed_tests/access_pmp_overlap/access_pmp_overlap.S +++ b/dv/uvm/core_ibex/directed_tests/access_pmp_overlap/access_pmp_overlap.S @@ -10,6 +10,10 @@ RVTEST_RV64M RVTEST_CODE_BEGIN + # setting machine handler + la t0, mtvec_handler + csrw mtvec, t0 + # setting the PMP region la t0, pmp_region_start srli t1, t0, PMP_SHIFT @@ -23,8 +27,14 @@ RVTEST_CODE_BEGIN # access across the boundary between PMP and non-PMP lw t1, -2(t0) + j pass + TEST_PASSFAIL +.balign 256 +mtvec_handler: + j fail + RVTEST_CODE_END .data diff --git a/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml b/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml index 7fd62a42..d1bcfdef 100644 --- a/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml +++ b/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml @@ -17,6 +17,9 @@ ld_script: link.ld includes: . gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ rtl_test: core_ibex_base_test rtl_params: PMPEnable: 1 @@ -28,3 +31,10 @@ iterations: 1 test_srcs: empty/empty.S config: base + +- test: access_pmp_overlap + desc: > + PMP access basic test + iterations: 1 + test_srcs: access_pmp_overlap/access_pmp_overlap.S + config: base diff --git a/dv/uvm/core_ibex/directed_tests/ibex_macros.h b/dv/uvm/core_ibex/directed_tests/ibex_macros.h index 2da545ab..ba89a422 100644 --- a/dv/uvm/core_ibex/directed_tests/ibex_macros.h +++ b/dv/uvm/core_ibex/directed_tests/ibex_macros.h @@ -1,3 +1,4 @@ +// Copyright lowRISC contributors. // Ibex specific macros #define SIGNATURE_ADDR 0x8ffffff8 diff --git a/dv/uvm/core_ibex/directed_tests/test_macros.h b/dv/uvm/core_ibex/directed_tests/test_macros.h deleted file mode 100644 index bfa2ab79..00000000 --- a/dv/uvm/core_ibex/directed_tests/test_macros.h +++ /dev/null @@ -1,754 +0,0 @@ -// See LICENSE for license details. -// clang-format off - -#ifndef __TEST_MACROS_SCALAR_H -#define __TEST_MACROS_SCALAR_H - - -#----------------------------------------------------------------------- -# Helper macros -#----------------------------------------------------------------------- - -#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) - -#define TEST_CASE( testnum, testreg, correctval, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - code; \ - li x7, MASK_XLEN(correctval); \ - bne testreg, x7, fail; - -# We use a macro hack to simpify code generation for various numbers -# of bubble cycles. - -#define TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 -#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 -#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 -#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 -#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 -#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 -#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 -#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 -#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 - - -#----------------------------------------------------------------------- -# RV64UI MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests for instructions with immediate operand -#----------------------------------------------------------------------- - -#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) - -#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x14, result, \ - li x1, MASK_XLEN(val1); \ - inst x14, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - inst x14, x1, SEXT_IMM(imm); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x14, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x14, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x14, x1, SEXT_IMM(imm); \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - inst x0, x1, SEXT_IMM(imm); \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register operands -#----------------------------------------------------------------------- - -#define TEST_R_OP( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x14, result, \ - li x1, val1; \ - inst x14, x1; \ - ) - -#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, val1; \ - inst x1, x1; \ - ) - -#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, val1; \ - inst x14, x1; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x14, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register-register operands -#----------------------------------------------------------------------- - -#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x14, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x14, x1, x2; \ - ) - -#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x1, x1, x2; \ - ) - -#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x2, x1, x2; \ - ) - -#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, x1; \ - ) - -#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x14, x1, x2; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x14, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x14, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x14, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x14, result, \ - li x4, 0; \ -1: li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x14, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x0, x1; \ - ) - -#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x1, x0; \ - ) - -#define TEST_RR_ZEROSRC12( testnum, inst, result ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, x0; \ - ) - -#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x0, x1, x2; \ - ) - -#----------------------------------------------------------------------- -# Test memory instructions -#----------------------------------------------------------------------- - -#define TEST_LD_OP( testnum, inst, result, offset, base ) \ - TEST_CASE( testnum, x14, result, \ - li x15, result; /* Tell the exception handler the expected result. */ \ - la x1, base; \ - inst x14, offset(x1); \ - ) - -#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ - TEST_CASE( testnum, x14, result, \ - la x1, base; \ - li x2, result; \ - la x15, 7f; /* Tell the exception handler how to skip this test. */ \ - store_inst x2, offset(x1); \ - load_inst x14, offset(x1); \ - j 8f; \ -7: \ - /* Set up the correct result for TEST_CASE(). */ \ - mv x14, x2; \ -8: \ - ) - -#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x1, base; \ - inst x14, offset(x1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x14, 0; \ - li x7, result; \ - bne x6, x7, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b; \ - -#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x1, base; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x14, offset(x1); \ - li x7, result; \ - bne x14, x7, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, result; \ - TEST_INSERT_NOPS_ ## src1_nops \ - la x2, base; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x14, offset(x2); \ - li x7, result; \ - bne x14, x7, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x2, base; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, result; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x14, offset(x2); \ - li x7, result; \ - bne x14, x7, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 2f; \ - bne x0, TESTNUM, fail; \ -1: bne x0, TESTNUM, 3f; \ -2: inst x1, x2, 1b; \ - bne x0, TESTNUM, fail; \ -3: - -#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 1f; \ - bne x0, TESTNUM, 2f; \ -1: bne x0, TESTNUM, fail; \ -2: inst x1, x2, 1b; \ -3: - -#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, val1; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, val2; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x2, val2; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, val1; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#----------------------------------------------------------------------- -# Test jump instructions -#----------------------------------------------------------------------- - -#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x6; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x13, x6, 0; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - - -#----------------------------------------------------------------------- -# RV64UF MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests floating-point instructions -#----------------------------------------------------------------------- - -#define qNaNh 0h:7e00 -#define sNaNh 0h:7c01 -#define qNaNf 0f:7fc00000 -#define sNaNf 0f:7f800001 -#define qNaN 0d:7ff8000000000000 -#define sNaN 0d:7ff0000000000001 - -#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - flh f0, 0(a0); \ - flh f1, 2(a0); \ - flh f2, 4(a0); \ - lh a3, 6(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 1; \ - test_ ## testnum ## _data: \ - .float16 val1; \ - .float16 val2; \ - .float16 val3; \ - .result; \ - .popsection - -#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - flw f0, 0(a0); \ - flw f1, 4(a0); \ - flw f2, 8(a0); \ - lw a3, 12(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 2; \ - test_ ## testnum ## _data: \ - .float val1; \ - .float val2; \ - .float val3; \ - .result; \ - .popsection - -#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - ld a3, 24(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .popsection - -// TODO: assign a separate mem location for the comparison address? -#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - lw a3, 24(a0); \ - lw t1, 28(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne t1, t2, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .popsection - -#define TEST_FCVT_S_D32( testnum, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_FCVT_S_D( testnum, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) - -#define TEST_FCVT_D_S( testnum, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ - fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) - -#define TEST_FCVT_H_S( testnum, result, val1 ) \ - TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ - fcvt.s.h f3, f0; fcvt.h.s f3, f3; fmv.x.h a0, f3) - -#define TEST_FCVT_H_D( testnum, result, val1 ) \ - TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ - fcvt.d.h f3, f0; fcvt.h.d f3, f3; fmv.x.h a0, f3) - - -#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.h a0, f3;) - -#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.h a0, f3) - -#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.s a0, f3) - -#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.h a0, f3) - -#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.d a0, f3) - -#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.s a0, f3) - -#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.h a0, f3) - -#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.d a0, f3) - -#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, f1; li t2, 0) - -#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1; li t2, 0) - -#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FCLASS_S(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ - fclass.s a0, fa0) - -#define TEST_FCLASS_D32(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, \ - la a0, test_ ## testnum ## _data ;\ - fld fa0, 0(a0); \ - fclass.d a0, fa0) \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .dword input; \ - .popsection - -#define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) - -#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.s a0, f0; \ - bne a0, a3, fail; \ - .pushsection .data; \ - .align 2; \ - test_ ## testnum ## _data: \ - .float result; \ - .popsection - -#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - lh a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.h a0, f0; \ - bne a0, a3, fail; \ - .pushsection .data; \ - .align 1; \ - test_ ## testnum ## _data: \ - .float16 result; \ - .popsection - -#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - lw a4, 4(a0); \ - li a1, val1; \ - inst f0, a1; \ - \ - fsd f0, 0(a0); \ - lw a1, 4(a0); \ - lw a0, 0(a0); \ - \ - fsflags x0; \ - bne a0, a3, fail; \ - bne a1, a4, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double result; \ - .popsection - -#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - ld a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.d a0, f0; \ - bne a0, a3, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double result; \ - .popsection - -// We need some special handling here to allow 64-bit comparison in 32-bit arch -// TODO: find a better name and clean up when intended for general usage? -#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \ -test_ ## testnum: \ - code; \ - la x15, test_ ## testnum ## _data ; \ - lw x7, 0(x15); \ - lw x15, 4(x15); \ - li TESTNUM, testnum; \ - bne testreg1, x7, fail;\ - bne testreg2, x15, fail;\ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .dword correctval; \ - .popsection - -// ^ x14 is used in some other macros, to avoid issues we use x15 for upper word - -#define MISALIGNED_LOAD_HANDLER \ - li t0, CAUSE_MISALIGNED_LOAD; \ - csrr t1, mcause; \ - bne t0, t1, fail; \ - \ - /* We got a misaligned exception. Pretend we handled it in software */ \ - /* by loading the correct result here. */ \ - mv a4, a5; \ - \ - /* And skip this instruction */ \ - csrr t0, mepc; \ - addi t0, t0, 4; \ - csrw mepc, t0; \ - mret - -#define MISALIGNED_STORE_HANDLER \ - li t0, CAUSE_MISALIGNED_STORE; \ - csrr t1, mcause; \ - bne t0, t1, fail; \ - \ - /* We got a misaligned exception. Skip this test. */ \ - csrw mepc, x15; \ - mret - -#----------------------------------------------------------------------- -# Pass and fail code (assumes test num is in TESTNUM) -#----------------------------------------------------------------------- - -#define TEST_PASSFAIL \ - bne x0, TESTNUM, pass; \ -fail: \ - RVTEST_FAIL; \ -pass: \ - RVTEST_PASS \ - - -#----------------------------------------------------------------------- -# Test data section -#----------------------------------------------------------------------- - -#define TEST_DATA - -#endif diff --git a/vendor/patches/riscv_test_env/changes.patch b/vendor/patches/riscv_test_env/changes.patch new file mode 100644 index 00000000..6fbcedc4 --- /dev/null +++ b/vendor/patches/riscv_test_env/changes.patch @@ -0,0 +1,89 @@ +diff --git a/p/riscv_test.h b/p/riscv_test.h +index fe14f086..18fdc0a7 100644 +--- a/p/riscv_test.h ++++ b/p/riscv_test.h +@@ -1,9 +1,11 @@ + // See LICENSE for license details. ++// clang-format off + + #ifndef _ENV_PHYSICAL_SINGLE_CORE_H + #define _ENV_PHYSICAL_SINGLE_CORE_H + +-#include "../encoding.h" ++#include "encoding.h" ++#include "ibex_macros.h" + + //----------------------------------------------------------------------- + // Begin Macro +@@ -190,14 +192,13 @@ handle_exception: \ + 1: ori TESTNUM, TESTNUM, 1337; \ + write_tohost: \ + sw TESTNUM, tohost, t5; \ +- sw zero, tohost + 4, t5; \ + j write_tohost; \ + reset_vector: \ + INIT_XREG; \ + RISCV_MULTICORE_DISABLE; \ +- INIT_SATP; \ ++ /*INIT_SATP; Ibex doesn't support supervisor mode */ \ + INIT_PMP; \ +- DELEGATE_NO_TRAPS; \ ++ /*DELEGATE_NO_TRAPS; Ibex doesn't support supervisor mode */ \ + li TESTNUM, 0; \ + la t0, trap_vector; \ + csrw mtvec, t0; \ +@@ -212,7 +213,7 @@ reset_vector: \ + (1 << CAUSE_MISALIGNED_FETCH) | \ + (1 << CAUSE_USER_ECALL) | \ + (1 << CAUSE_BREAKPOINT); \ +- csrw medeleg, t0; \ ++ /*csrw medeleg, t0; Ibex doesn't support supervisor mode */ \ + 1: csrwi mstatus, 0; \ + init; \ + EXTRA_INIT; \ +@@ -236,20 +237,24 @@ reset_vector: \ + + #define RVTEST_PASS \ + fence; \ +- li TESTNUM, 1; \ +- li a7, 93; \ +- li a0, 0; \ +- ecall ++ li x2, SIGNATURE_ADDR; \ ++ li x1, (FINISHED_IRQ << 8) | CORE_STATUS; \ ++ sw x1, 0(x2); \ ++ li x1, (TEST_PASS << 8) | TEST_RESULT; \ ++ sw x1, 0(x2); \ ++ 2:; \ ++ j 2b; + + #define TESTNUM gp + #define RVTEST_FAIL \ + fence; \ +-1: beqz TESTNUM, 1b; \ +- sll TESTNUM, TESTNUM, 1; \ +- or TESTNUM, TESTNUM, 1; \ +- li a7, 93; \ +- addi a0, TESTNUM, 0; \ +- ecall ++ li x2, SIGNATURE_ADDR; \ ++ li x1, (FINISHED_IRQ << 8) | CORE_STATUS; \ ++ sw x1, 0(x2); \ ++ li x1, (TEST_FAIL << 8) | TEST_RESULT; \ ++ sw x1, 0(x2); \ ++ 2:; \ ++ j 2b; + + //----------------------------------------------------------------------- + // Data Section Macro +@@ -260,8 +265,8 @@ reset_vector: \ + #define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .pushsection .tohost,"aw",@progbits; \ +- .align 6; .global tohost; tohost: .dword 0; .size tohost, 8; \ +- .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8;\ ++ .align 6; .global tohost; tohost: .dword 0; \ ++ .align 6; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 4; .global begin_signature; begin_signature: + diff --git a/vendor/riscv-test-env/LICENSE b/vendor/riscv-test-env/LICENSE new file mode 100644 index 00000000..48fe522a --- /dev/null +++ b/vendor/riscv-test-env/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2012-2015, The Regents of the University of California (Regents). +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/dv/uvm/core_ibex/directed_tests/encoding.h b/vendor/riscv-test-env/encoding.h similarity index 73% rename from dv/uvm/core_ibex/directed_tests/encoding.h rename to vendor/riscv-test-env/encoding.h index f21b45bb..2aa895b8 100644 --- a/dv/uvm/core_ibex/directed_tests/encoding.h +++ b/vendor/riscv-test-env/encoding.h @@ -3,143 +3,114 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -// Ibex specific macros -#define SIGNATURE_ADDR 0x8ffffff8 +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 -// signatue type - should be stored at sign_addr[7:0] -#define CORE_STATUS 0x0 -#define TEST_RESULT 0x1 -#define WRITE_GPR 0x2 -#define WRITE_CSR 0x3 +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 -// core status - should be stored at sign_addr[12:8] -#define INITIALIZED 0x0 -#define IN_DEBUG_MODE 0x1 -#define IN_MACHINE_MODE 0x2 -#define IN_HYPERVISOR_MODE 0x3 -#define IN_SUPERVISOR_MODE 0x4 -#define IN_USER_MODE 0x5 -#define HANDLING_IRQ 0x6 -#define FINISHED_IRQ 0x7 -#define HANDLING_EXCEPTION 0x8 -#define INSTR_FAULT_EXCEPTION 0x9 -#define ILLEGAL_INSTR_EXCEPTION 0xa -#define LOAD_FAULT_EXCEPTION 0xb -#define STORE_FAULT_EXCEPTION 0xc -#define EBREAK_EXCEPTION 0xd +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 -// test result - should be stored at sign_addr[8] -#define TEST_PASS 0x0 -#define TEST_FAIL 0x1 +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1 << 29) -#define DCSR_FULLRESET (1 << 28) -#define DCSR_EBREAKM (1 << 15) -#define DCSR_EBREAKH (1 << 14) -#define DCSR_EBREAKS (1 << 13) -#define DCSR_EBREAKU (1 << 12) -#define DCSR_STOPCYCLE (1 << 10) -#define DCSR_STOPTIME (1 << 9) -#define DCSR_CAUSE (7 << 6) -#define DCSR_DEBUGINT (1 << 5) -#define DCSR_HALT (1 << 3) -#define DCSR_STEP (1 << 2) -#define DCSR_PRV (3 << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) -#define MCONTROL_SELECT (1 << 19) -#define MCONTROL_TIMING (1 << 18) -#define MCONTROL_ACTION (0x3f << 12) -#define MCONTROL_CHAIN (1 << 11) -#define MCONTROL_MATCH (0xf << 7) -#define MCONTROL_M (1 << 6) -#define MCONTROL_H (1 << 5) -#define MCONTROL_S (1 << 4) -#define MCONTROL_U (1 << 3) -#define MCONTROL_EXECUTE (1 << 2) -#define MCONTROL_STORE (1 << 1) -#define MCONTROL_LOAD (1 << 0) +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP @@ -151,64 +122,64 @@ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF +#define SATP32_PPN 0x003FFFFF #define SATP64_MODE 0xF000000000000000 #define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF +#define SATP64_PPN 0x00000FFFFFFFFFFF -#define SATP_MODE_OFF 0 +#define SATP_MODE_OFF 0 #define SATP_MODE_SV32 1 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 #define SATP_MODE_SV57 10 #define SATP_MODE_SV64 11 -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 #define PMP_SHIFT 2 -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 #define PMP_NAPOT 0x18 -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 /* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ #define PTE_PPN_SHIFT 10 @@ -217,15 +188,15 @@ #ifdef __riscv #if __riscv_xlen == 64 -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#define SATP_MODE SATP64_MODE +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE #else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#define SATP_MODE SATP32_MODE +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -234,35 +205,24 @@ #ifdef __GNUC__ -#define read_csr(reg) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; \ - }) +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) -#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); }) +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) -#define swap_csr(reg, val) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; \ - }) +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) -#define set_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; \ - }) +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) -#define clear_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; \ - }) +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) @@ -279,1347 +239,1347 @@ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H #define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f +#define MASK_SLLI_RV32 0xfe00707f #define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f +#define MASK_SRLI_RV32 0xfe00707f #define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f +#define MASK_SRAI_RV32 0xfe00707f #define MATCH_FRFLAGS 0x102073 -#define MASK_FRFLAGS 0xfffff07f +#define MASK_FRFLAGS 0xfffff07f #define MATCH_FSFLAGS 0x101073 -#define MASK_FSFLAGS 0xfff0707f +#define MASK_FSFLAGS 0xfff0707f #define MATCH_FSFLAGSI 0x105073 -#define MASK_FSFLAGSI 0xfff0707f +#define MASK_FSFLAGSI 0xfff0707f #define MATCH_FRRM 0x202073 -#define MASK_FRRM 0xfffff07f +#define MASK_FRRM 0xfffff07f #define MATCH_FSRM 0x201073 -#define MASK_FSRM 0xfff0707f +#define MASK_FSRM 0xfff0707f #define MATCH_FSRMI 0x205073 -#define MASK_FSRMI 0xfff0707f +#define MASK_FSRMI 0xfff0707f #define MATCH_FSCSR 0x301073 -#define MASK_FSCSR 0xfff0707f +#define MASK_FSCSR 0xfff0707f #define MATCH_FRCSR 0x302073 -#define MASK_FRCSR 0xfffff07f +#define MASK_FRCSR 0xfffff07f #define MATCH_RDCYCLE 0xc0002073 -#define MASK_RDCYCLE 0xfffff07f +#define MASK_RDCYCLE 0xfffff07f #define MATCH_RDTIME 0xc0102073 -#define MASK_RDTIME 0xfffff07f +#define MASK_RDTIME 0xfffff07f #define MATCH_RDINSTRET 0xc0202073 -#define MASK_RDINSTRET 0xfffff07f +#define MASK_RDINSTRET 0xfffff07f #define MATCH_RDCYCLEH 0xc8002073 -#define MASK_RDCYCLEH 0xfffff07f +#define MASK_RDCYCLEH 0xfffff07f #define MATCH_RDTIMEH 0xc8102073 -#define MASK_RDTIMEH 0xfffff07f +#define MASK_RDTIMEH 0xfffff07f #define MATCH_RDINSTRETH 0xc8202073 -#define MASK_RDINSTRETH 0xfffff07f +#define MASK_RDINSTRETH 0xfffff07f #define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff +#define MASK_SCALL 0xffffffff #define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff +#define MASK_SBREAK 0xffffffff #define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f +#define MASK_FMV_X_S 0xfff0707f #define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f +#define MASK_FMV_S_X 0xfff0707f #define MATCH_FENCE_TSO 0x8330000f -#define MASK_FENCE_TSO 0xfff0707f +#define MASK_FENCE_TSO 0xfff0707f #define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff +#define MASK_PAUSE 0xffffffff #define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f +#define MASK_BEQ 0x707f #define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f +#define MASK_BNE 0x707f #define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f +#define MASK_BLT 0x707f #define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f +#define MASK_BGE 0x707f #define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f +#define MASK_BLTU 0x707f #define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f +#define MASK_BGEU 0x707f #define MATCH_JALR 0x67 -#define MASK_JALR 0x707f +#define MASK_JALR 0x707f #define MATCH_JAL 0x6f -#define MASK_JAL 0x7f +#define MASK_JAL 0x7f #define MATCH_LUI 0x37 -#define MASK_LUI 0x7f +#define MASK_LUI 0x7f #define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f +#define MASK_AUIPC 0x7f #define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f +#define MASK_ADDI 0x707f #define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f +#define MASK_SLLI 0xfc00707f #define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f +#define MASK_SLTI 0x707f #define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f +#define MASK_SLTIU 0x707f #define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f +#define MASK_XORI 0x707f #define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f +#define MASK_SRLI 0xfc00707f #define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f +#define MASK_SRAI 0xfc00707f #define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f +#define MASK_ORI 0x707f #define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f +#define MASK_ANDI 0x707f #define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f +#define MASK_ADD 0xfe00707f #define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f +#define MASK_SUB 0xfe00707f #define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f +#define MASK_SLL 0xfe00707f #define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f +#define MASK_SLT 0xfe00707f #define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f +#define MASK_SLTU 0xfe00707f #define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f +#define MASK_XOR 0xfe00707f #define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f +#define MASK_SRL 0xfe00707f #define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f +#define MASK_SRA 0xfe00707f #define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f +#define MASK_OR 0xfe00707f #define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f +#define MASK_AND 0xfe00707f #define MATCH_LB 0x3 -#define MASK_LB 0x707f +#define MASK_LB 0x707f #define MATCH_LH 0x1003 -#define MASK_LH 0x707f +#define MASK_LH 0x707f #define MATCH_LW 0x2003 -#define MASK_LW 0x707f +#define MASK_LW 0x707f #define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f +#define MASK_LBU 0x707f #define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f +#define MASK_LHU 0x707f #define MATCH_SB 0x23 -#define MASK_SB 0x707f +#define MASK_SB 0x707f #define MATCH_SH 0x1023 -#define MASK_SH 0x707f +#define MASK_SH 0x707f #define MATCH_SW 0x2023 -#define MASK_SW 0x707f +#define MASK_SW 0x707f #define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f +#define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f +#define MASK_FENCE_I 0x707f #define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f +#define MASK_ADDIW 0x707f #define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f +#define MASK_SLLIW 0xfe00707f #define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f +#define MASK_SRLIW 0xfe00707f #define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f +#define MASK_SRAIW 0xfe00707f #define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f +#define MASK_ADDW 0xfe00707f #define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f +#define MASK_SUBW 0xfe00707f #define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f +#define MASK_SLLW 0xfe00707f #define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f +#define MASK_SRLW 0xfe00707f #define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f +#define MASK_SRAW 0xfe00707f #define MATCH_LD 0x3003 -#define MASK_LD 0x707f +#define MASK_LD 0x707f #define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f +#define MASK_LWU 0x707f #define MATCH_SD 0x3023 -#define MASK_SD 0x707f +#define MASK_SD 0x707f #define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f +#define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f +#define MASK_MULH 0xfe00707f #define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f +#define MASK_MULHSU 0xfe00707f #define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f +#define MASK_MULHU 0xfe00707f #define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f +#define MASK_DIV 0xfe00707f #define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f +#define MASK_DIVU 0xfe00707f #define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f +#define MASK_REM 0xfe00707f #define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f +#define MASK_REMU 0xfe00707f #define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f +#define MASK_MULW 0xfe00707f #define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f +#define MASK_DIVW 0xfe00707f #define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f +#define MASK_DIVUW 0xfe00707f #define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f +#define MASK_REMW 0xfe00707f #define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f +#define MASK_REMUW 0xfe00707f #define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f +#define MASK_AMOADD_W 0xf800707f #define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f +#define MASK_AMOXOR_W 0xf800707f #define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f +#define MASK_AMOOR_W 0xf800707f #define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f +#define MASK_AMOAND_W 0xf800707f #define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f +#define MASK_AMOMIN_W 0xf800707f #define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f +#define MASK_AMOMAX_W 0xf800707f #define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f +#define MASK_AMOMINU_W 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f +#define MASK_AMOMAXU_W 0xf800707f #define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f +#define MASK_AMOSWAP_W 0xf800707f #define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f +#define MASK_LR_W 0xf9f0707f #define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f +#define MASK_SC_W 0xf800707f #define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f +#define MASK_AMOADD_D 0xf800707f #define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f +#define MASK_AMOXOR_D 0xf800707f #define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f +#define MASK_AMOOR_D 0xf800707f #define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f +#define MASK_AMOAND_D 0xf800707f #define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f +#define MASK_AMOMIN_D 0xf800707f #define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f +#define MASK_AMOMAX_D 0xf800707f #define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f +#define MASK_AMOMINU_D 0xf800707f #define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f +#define MASK_AMOMAXU_D 0xf800707f #define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f +#define MASK_AMOSWAP_D 0xf800707f #define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f +#define MASK_LR_D 0xf9f0707f #define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f +#define MASK_SC_D 0xf800707f #define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f +#define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f +#define MASK_FSUB_S 0xfe00007f #define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f +#define MASK_FMUL_S 0xfe00007f #define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f +#define MASK_FDIV_S 0xfe00007f #define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f +#define MASK_FSGNJ_S 0xfe00707f #define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f +#define MASK_FSGNJN_S 0xfe00707f #define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f +#define MASK_FSGNJX_S 0xfe00707f #define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f +#define MASK_FMIN_S 0xfe00707f #define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f +#define MASK_FMAX_S 0xfe00707f #define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f +#define MASK_FSQRT_S 0xfff0007f #define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f +#define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f +#define MASK_FLT_S 0xfe00707f #define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f +#define MASK_FEQ_S 0xfe00707f #define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f +#define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f +#define MASK_FCVT_WU_S 0xfff0007f #define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f +#define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f +#define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f +#define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f +#define MASK_FCVT_S_WU 0xfff0007f #define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f +#define MASK_FMV_W_X 0xfff0707f #define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f +#define MASK_FLW 0x707f #define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f +#define MASK_FSW 0x707f #define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f +#define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f +#define MASK_FMSUB_S 0x600007f #define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f +#define MASK_FNMSUB_S 0x600007f #define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f +#define MASK_FNMADD_S 0x600007f #define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f +#define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f +#define MASK_FCVT_LU_S 0xfff0007f #define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f +#define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f +#define MASK_FCVT_S_LU 0xfff0007f #define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f +#define MASK_FADD_D 0xfe00007f #define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f +#define MASK_FSUB_D 0xfe00007f #define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f +#define MASK_FMUL_D 0xfe00007f #define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f +#define MASK_FDIV_D 0xfe00007f #define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f +#define MASK_FSGNJ_D 0xfe00707f #define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f +#define MASK_FSGNJN_D 0xfe00707f #define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f +#define MASK_FSGNJX_D 0xfe00707f #define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f +#define MASK_FMIN_D 0xfe00707f #define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f +#define MASK_FMAX_D 0xfe00707f #define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f +#define MASK_FCVT_S_D 0xfff0007f #define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f +#define MASK_FCVT_D_S 0xfff0007f #define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f +#define MASK_FSQRT_D 0xfff0007f #define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f +#define MASK_FLE_D 0xfe00707f #define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f +#define MASK_FLT_D 0xfe00707f #define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f +#define MASK_FEQ_D 0xfe00707f #define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f +#define MASK_FCVT_W_D 0xfff0007f #define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f +#define MASK_FCVT_WU_D 0xfff0007f #define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f +#define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f +#define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f +#define MASK_FCVT_D_WU 0xfff0007f #define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f +#define MASK_FLD 0x707f #define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f +#define MASK_FSD 0x707f #define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f +#define MASK_FMADD_D 0x600007f #define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f +#define MASK_FMSUB_D 0x600007f #define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f +#define MASK_FNMSUB_D 0x600007f #define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f +#define MASK_FNMADD_D 0x600007f #define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f +#define MASK_FCVT_L_D 0xfff0007f #define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f +#define MASK_FCVT_LU_D 0xfff0007f #define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f +#define MASK_FMV_X_D 0xfff0707f #define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f +#define MASK_FCVT_D_L 0xfff0007f #define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f +#define MASK_FCVT_D_LU 0xfff0007f #define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f +#define MASK_FMV_D_X 0xfff0707f #define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f +#define MASK_FADD_Q 0xfe00007f #define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f +#define MASK_FSUB_Q 0xfe00007f #define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f +#define MASK_FMUL_Q 0xfe00007f #define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f +#define MASK_FDIV_Q 0xfe00007f #define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f +#define MASK_FSGNJ_Q 0xfe00707f #define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f +#define MASK_FSGNJN_Q 0xfe00707f #define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f +#define MASK_FSGNJX_Q 0xfe00707f #define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f +#define MASK_FMIN_Q 0xfe00707f #define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f +#define MASK_FMAX_Q 0xfe00707f #define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f +#define MASK_FCVT_S_Q 0xfff0007f #define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f +#define MASK_FCVT_Q_S 0xfff0007f #define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f +#define MASK_FCVT_D_Q 0xfff0007f #define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f +#define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f +#define MASK_FSQRT_Q 0xfff0007f #define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f +#define MASK_FLE_Q 0xfe00707f #define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f +#define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f +#define MASK_FEQ_Q 0xfe00707f #define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f +#define MASK_FCVT_W_Q 0xfff0007f #define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f +#define MASK_FCVT_WU_Q 0xfff0007f #define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f +#define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f +#define MASK_FCVT_Q_W 0xfff0007f #define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f +#define MASK_FCVT_Q_WU 0xfff0007f #define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f +#define MASK_FLQ 0x707f #define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f +#define MASK_FSQ 0x707f #define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f +#define MASK_FMADD_Q 0x600007f #define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f +#define MASK_FMSUB_Q 0x600007f #define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f +#define MASK_FNMSUB_Q 0x600007f #define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f +#define MASK_FNMADD_Q 0x600007f #define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f +#define MASK_FCVT_L_Q 0xfff0007f #define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f +#define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f +#define MASK_FCVT_Q_L 0xfff0007f #define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f +#define MASK_FCVT_Q_LU 0xfff0007f #define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f +#define MASK_FMV_X_Q 0xfff0707f #define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f +#define MASK_FMV_Q_X 0xfff0707f #define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff +#define MASK_ECALL 0xffffffff #define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff +#define MASK_EBREAK 0xffffffff #define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff +#define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff +#define MASK_SRET 0xffffffff #define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff +#define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff +#define MASK_DRET 0xffffffff #define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff +#define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f +#define MASK_CSRRW 0x707f #define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f +#define MASK_CSRRS 0x707f #define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f +#define MASK_CSRRC 0x707f #define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f +#define MASK_CSRRWI 0x707f #define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f +#define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f +#define MASK_CSRRCI 0x707f #define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff +#define MASK_HFENCE_VVMA 0xfe007fff #define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff +#define MASK_HFENCE_GVMA 0xfe007fff #define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff +#define MASK_C_NOP 0xffff #define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 +#define MASK_C_ADDI16SP 0xef83 #define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f +#define MASK_C_JR 0xf07f #define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f +#define MASK_C_JALR 0xf07f #define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff +#define MASK_C_EBREAK 0xffff #define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 +#define MASK_C_ADDI4SPN 0xe003 #define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 +#define MASK_C_FLD 0xe003 #define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 +#define MASK_C_LW 0xe003 #define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 +#define MASK_C_FLW 0xe003 #define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 +#define MASK_C_FSD 0xe003 #define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 +#define MASK_C_SW 0xe003 #define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 +#define MASK_C_FSW 0xe003 #define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 +#define MASK_C_ADDI 0xe003 #define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 +#define MASK_C_JAL 0xe003 #define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 +#define MASK_C_LI 0xe003 #define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 +#define MASK_C_LUI 0xe003 #define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 +#define MASK_C_SRLI 0xec03 #define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 +#define MASK_C_SRAI 0xec03 #define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 +#define MASK_C_ANDI 0xec03 #define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 +#define MASK_C_SUB 0xfc63 #define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 +#define MASK_C_XOR 0xfc63 #define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 +#define MASK_C_OR 0xfc63 #define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 +#define MASK_C_AND 0xfc63 #define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 +#define MASK_C_J 0xe003 #define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 +#define MASK_C_BEQZ 0xe003 #define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 +#define MASK_C_BNEZ 0xe003 #define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 +#define MASK_C_SLLI 0xe003 #define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 +#define MASK_C_FLDSP 0xe003 #define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 +#define MASK_C_LWSP 0xe003 #define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 +#define MASK_C_FLWSP 0xe003 #define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 +#define MASK_C_MV 0xf003 #define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 +#define MASK_C_ADD 0xf003 #define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 +#define MASK_C_FSDSP 0xe003 #define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 +#define MASK_C_SWSP 0xe003 #define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 +#define MASK_C_FSWSP 0xe003 #define MATCH_C_SRLI_RV32 0x8001 -#define MASK_C_SRLI_RV32 0xfc03 +#define MASK_C_SRLI_RV32 0xfc03 #define MATCH_C_SRAI_RV32 0x8401 -#define MASK_C_SRAI_RV32 0xfc03 +#define MASK_C_SRAI_RV32 0xfc03 #define MATCH_C_SLLI_RV32 0x2 -#define MASK_C_SLLI_RV32 0xf003 +#define MASK_C_SLLI_RV32 0xf003 #define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 +#define MASK_C_LD 0xe003 #define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 +#define MASK_C_SD 0xe003 #define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 +#define MASK_C_SUBW 0xfc63 #define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 +#define MASK_C_ADDW 0xfc63 #define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 +#define MASK_C_ADDIW 0xe003 #define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 +#define MASK_C_LDSP 0xe003 #define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 +#define MASK_C_SDSP 0xe003 #define MATCH_C_LQ 0x2000 -#define MASK_C_LQ 0xe003 +#define MASK_C_LQ 0xe003 #define MATCH_C_SQ 0xa000 -#define MASK_C_SQ 0xe003 +#define MASK_C_SQ 0xe003 #define MATCH_C_LQSP 0x2002 -#define MASK_C_LQSP 0xe003 +#define MASK_C_LQSP 0xe003 #define MATCH_C_SQSP 0xa002 -#define MASK_C_SQSP 0xe003 +#define MASK_C_SQSP 0xe003 #define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f +#define MASK_CUSTOM0 0x707f #define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f +#define MASK_CUSTOM0_RS1 0x707f #define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MASK_CUSTOM0_RS1_RS2 0x707f #define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f +#define MASK_CUSTOM0_RD 0x707f #define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f +#define MASK_CUSTOM0_RD_RS1 0x707f #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f #define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f +#define MASK_CUSTOM1 0x707f #define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f +#define MASK_CUSTOM1_RS1 0x707f #define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MASK_CUSTOM1_RS1_RS2 0x707f #define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f +#define MASK_CUSTOM1_RD 0x707f #define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f +#define MASK_CUSTOM1_RD_RS1 0x707f #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f #define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f +#define MASK_CUSTOM2 0x707f #define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f +#define MASK_CUSTOM2_RS1 0x707f #define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MASK_CUSTOM2_RS1_RS2 0x707f #define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f +#define MASK_CUSTOM2_RD 0x707f #define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f +#define MASK_CUSTOM2_RD_RS1 0x707f #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f #define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f +#define MASK_CUSTOM3 0x707f #define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f +#define MASK_CUSTOM3_RS1 0x707f #define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MASK_CUSTOM3_RS1_RS2 0x707f #define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f +#define MASK_CUSTOM3_RD 0x707f #define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f +#define MASK_CUSTOM3_RD_RS1 0x707f #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f #define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f +#define MASK_VSETVLI 0x8000707f #define MATCH_VSETVL 0x80007057 -#define MASK_VSETVL 0xfe00707f +#define MASK_VSETVL 0xfe00707f #define MATCH_VLB_V 0x10000007 -#define MASK_VLB_V 0x1df0707f +#define MASK_VLB_V 0x1df0707f #define MATCH_VLH_V 0x10005007 -#define MASK_VLH_V 0x1df0707f +#define MASK_VLH_V 0x1df0707f #define MATCH_VLW_V 0x10006007 -#define MASK_VLW_V 0x1df0707f +#define MASK_VLW_V 0x1df0707f #define MATCH_VLE_V 0x7007 -#define MASK_VLE_V 0x1df0707f +#define MASK_VLE_V 0x1df0707f #define MATCH_VLBU_V 0x7 -#define MASK_VLBU_V 0x1df0707f +#define MASK_VLBU_V 0x1df0707f #define MATCH_VLHU_V 0x5007 -#define MASK_VLHU_V 0x1df0707f +#define MASK_VLHU_V 0x1df0707f #define MATCH_VLWU_V 0x6007 -#define MASK_VLWU_V 0x1df0707f +#define MASK_VLWU_V 0x1df0707f #define MATCH_VSB_V 0x27 -#define MASK_VSB_V 0x1df0707f +#define MASK_VSB_V 0x1df0707f #define MATCH_VSH_V 0x5027 -#define MASK_VSH_V 0x1df0707f +#define MASK_VSH_V 0x1df0707f #define MATCH_VSW_V 0x6027 -#define MASK_VSW_V 0x1df0707f +#define MASK_VSW_V 0x1df0707f #define MATCH_VSE_V 0x7027 -#define MASK_VSE_V 0x1df0707f +#define MASK_VSE_V 0x1df0707f #define MATCH_VLSB_V 0x18000007 -#define MASK_VLSB_V 0x1c00707f +#define MASK_VLSB_V 0x1c00707f #define MATCH_VLSH_V 0x18005007 -#define MASK_VLSH_V 0x1c00707f +#define MASK_VLSH_V 0x1c00707f #define MATCH_VLSW_V 0x18006007 -#define MASK_VLSW_V 0x1c00707f +#define MASK_VLSW_V 0x1c00707f #define MATCH_VLSE_V 0x8007007 -#define MASK_VLSE_V 0x1c00707f +#define MASK_VLSE_V 0x1c00707f #define MATCH_VLSBU_V 0x8000007 -#define MASK_VLSBU_V 0x1c00707f +#define MASK_VLSBU_V 0x1c00707f #define MATCH_VLSHU_V 0x8005007 -#define MASK_VLSHU_V 0x1c00707f +#define MASK_VLSHU_V 0x1c00707f #define MATCH_VLSWU_V 0x8006007 -#define MASK_VLSWU_V 0x1c00707f +#define MASK_VLSWU_V 0x1c00707f #define MATCH_VSSB_V 0x8000027 -#define MASK_VSSB_V 0x1c00707f +#define MASK_VSSB_V 0x1c00707f #define MATCH_VSSH_V 0x8005027 -#define MASK_VSSH_V 0x1c00707f +#define MASK_VSSH_V 0x1c00707f #define MATCH_VSSW_V 0x8006027 -#define MASK_VSSW_V 0x1c00707f +#define MASK_VSSW_V 0x1c00707f #define MATCH_VSSE_V 0x8007027 -#define MASK_VSSE_V 0x1c00707f +#define MASK_VSSE_V 0x1c00707f #define MATCH_VLXB_V 0x1c000007 -#define MASK_VLXB_V 0x1c00707f +#define MASK_VLXB_V 0x1c00707f #define MATCH_VLXH_V 0x1c005007 -#define MASK_VLXH_V 0x1c00707f +#define MASK_VLXH_V 0x1c00707f #define MATCH_VLXW_V 0x1c006007 -#define MASK_VLXW_V 0x1c00707f +#define MASK_VLXW_V 0x1c00707f #define MATCH_VLXE_V 0xc007007 -#define MASK_VLXE_V 0x1c00707f +#define MASK_VLXE_V 0x1c00707f #define MATCH_VLXBU_V 0xc000007 -#define MASK_VLXBU_V 0x1c00707f +#define MASK_VLXBU_V 0x1c00707f #define MATCH_VLXHU_V 0xc005007 -#define MASK_VLXHU_V 0x1c00707f +#define MASK_VLXHU_V 0x1c00707f #define MATCH_VLXWU_V 0xc006007 -#define MASK_VLXWU_V 0x1c00707f +#define MASK_VLXWU_V 0x1c00707f #define MATCH_VSXB_V 0xc000027 -#define MASK_VSXB_V 0x1c00707f +#define MASK_VSXB_V 0x1c00707f #define MATCH_VSXH_V 0xc005027 -#define MASK_VSXH_V 0x1c00707f +#define MASK_VSXH_V 0x1c00707f #define MATCH_VSXW_V 0xc006027 -#define MASK_VSXW_V 0x1c00707f +#define MASK_VSXW_V 0x1c00707f #define MATCH_VSXE_V 0xc007027 -#define MASK_VSXE_V 0x1c00707f +#define MASK_VSXE_V 0x1c00707f #define MATCH_VSUXB_V 0x1c000027 -#define MASK_VSUXB_V 0xfc00707f +#define MASK_VSUXB_V 0xfc00707f #define MATCH_VSUXH_V 0x1c005027 -#define MASK_VSUXH_V 0xfc00707f +#define MASK_VSUXH_V 0xfc00707f #define MATCH_VSUXW_V 0x1c006027 -#define MASK_VSUXW_V 0xfc00707f +#define MASK_VSUXW_V 0xfc00707f #define MATCH_VSUXE_V 0x1c007027 -#define MASK_VSUXE_V 0xfc00707f +#define MASK_VSUXE_V 0xfc00707f #define MATCH_VLBFF_V 0x11000007 -#define MASK_VLBFF_V 0x1df0707f +#define MASK_VLBFF_V 0x1df0707f #define MATCH_VLHFF_V 0x11005007 -#define MASK_VLHFF_V 0x1df0707f +#define MASK_VLHFF_V 0x1df0707f #define MATCH_VLWFF_V 0x11006007 -#define MASK_VLWFF_V 0x1df0707f +#define MASK_VLWFF_V 0x1df0707f #define MATCH_VLEFF_V 0x1007007 -#define MASK_VLEFF_V 0x1df0707f +#define MASK_VLEFF_V 0x1df0707f #define MATCH_VLBUFF_V 0x1000007 -#define MASK_VLBUFF_V 0x1df0707f +#define MASK_VLBUFF_V 0x1df0707f #define MATCH_VLHUFF_V 0x1005007 -#define MASK_VLHUFF_V 0x1df0707f +#define MASK_VLHUFF_V 0x1df0707f #define MATCH_VLWUFF_V 0x1006007 -#define MASK_VLWUFF_V 0x1df0707f +#define MASK_VLWUFF_V 0x1df0707f #define MATCH_VL1R_V 0x2807007 -#define MASK_VL1R_V 0xfff0707f +#define MASK_VL1R_V 0xfff0707f #define MATCH_VS1R_V 0x2807027 -#define MASK_VS1R_V 0xfff0707f +#define MASK_VS1R_V 0xfff0707f #define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f +#define MASK_VFADD_VF 0xfc00707f #define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f +#define MASK_VFSUB_VF 0xfc00707f #define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f +#define MASK_VFMIN_VF 0xfc00707f #define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f +#define MASK_VFMAX_VF 0xfc00707f #define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f +#define MASK_VFSGNJ_VF 0xfc00707f #define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f +#define MASK_VFSGNJN_VF 0xfc00707f #define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f +#define MASK_VFSGNJX_VF 0xfc00707f #define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MASK_VFSLIDE1UP_VF 0xfc00707f #define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f #define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f +#define MASK_VFMV_S_F 0xfff0707f #define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f +#define MASK_VFMERGE_VFM 0xfe00707f #define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f +#define MASK_VFMV_V_F 0xfff0707f #define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f +#define MASK_VMFEQ_VF 0xfc00707f #define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f +#define MASK_VMFLE_VF 0xfc00707f #define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f +#define MASK_VMFLT_VF 0xfc00707f #define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f +#define MASK_VMFNE_VF 0xfc00707f #define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f +#define MASK_VMFGT_VF 0xfc00707f #define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f +#define MASK_VMFGE_VF 0xfc00707f #define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f +#define MASK_VFDIV_VF 0xfc00707f #define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f +#define MASK_VFRDIV_VF 0xfc00707f #define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f +#define MASK_VFMUL_VF 0xfc00707f #define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f +#define MASK_VFRSUB_VF 0xfc00707f #define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f +#define MASK_VFMADD_VF 0xfc00707f #define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f +#define MASK_VFNMADD_VF 0xfc00707f #define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f +#define MASK_VFMSUB_VF 0xfc00707f #define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f +#define MASK_VFNMSUB_VF 0xfc00707f #define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f +#define MASK_VFMACC_VF 0xfc00707f #define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f +#define MASK_VFNMACC_VF 0xfc00707f #define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f +#define MASK_VFMSAC_VF 0xfc00707f #define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f +#define MASK_VFNMSAC_VF 0xfc00707f #define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f +#define MASK_VFWADD_VF 0xfc00707f #define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f +#define MASK_VFWSUB_VF 0xfc00707f #define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f +#define MASK_VFWADD_WF 0xfc00707f #define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f +#define MASK_VFWSUB_WF 0xfc00707f #define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f +#define MASK_VFWMUL_VF 0xfc00707f #define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f +#define MASK_VFWMACC_VF 0xfc00707f #define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f +#define MASK_VFWNMACC_VF 0xfc00707f #define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f +#define MASK_VFWMSAC_VF 0xfc00707f #define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f +#define MASK_VFWNMSAC_VF 0xfc00707f #define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f +#define MASK_VFADD_VV 0xfc00707f #define MATCH_VFREDSUM_VS 0x4001057 -#define MASK_VFREDSUM_VS 0xfc00707f +#define MASK_VFREDSUM_VS 0xfc00707f #define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f +#define MASK_VFSUB_VV 0xfc00707f #define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f +#define MASK_VFREDOSUM_VS 0xfc00707f #define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f +#define MASK_VFMIN_VV 0xfc00707f #define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f +#define MASK_VFREDMIN_VS 0xfc00707f #define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f +#define MASK_VFMAX_VV 0xfc00707f #define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f +#define MASK_VFREDMAX_VS 0xfc00707f #define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f +#define MASK_VFSGNJ_VV 0xfc00707f #define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f +#define MASK_VFSGNJN_VV 0xfc00707f #define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f +#define MASK_VFSGNJX_VV 0xfc00707f #define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f +#define MASK_VFMV_F_S 0xfe0ff07f #define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f +#define MASK_VMFEQ_VV 0xfc00707f #define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f +#define MASK_VMFLE_VV 0xfc00707f #define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f +#define MASK_VMFLT_VV 0xfc00707f #define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f +#define MASK_VMFNE_VV 0xfc00707f #define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f +#define MASK_VFDIV_VV 0xfc00707f #define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f +#define MASK_VFMUL_VV 0xfc00707f #define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f +#define MASK_VFMADD_VV 0xfc00707f #define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f +#define MASK_VFNMADD_VV 0xfc00707f #define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f +#define MASK_VFMSUB_VV 0xfc00707f #define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f +#define MASK_VFNMSUB_VV 0xfc00707f #define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f +#define MASK_VFMACC_VV 0xfc00707f #define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f +#define MASK_VFNMACC_VV 0xfc00707f #define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f +#define MASK_VFMSAC_VV 0xfc00707f #define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f +#define MASK_VFNMSAC_VV 0xfc00707f #define MATCH_VFCVT_XU_F_V 0x88001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MASK_VFCVT_XU_F_V 0xfc0ff07f #define MATCH_VFCVT_X_F_V 0x88009057 -#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MASK_VFCVT_X_F_V 0xfc0ff07f #define MATCH_VFCVT_F_XU_V 0x88011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MASK_VFCVT_F_XU_V 0xfc0ff07f #define MATCH_VFCVT_F_X_V 0x88019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MASK_VFCVT_F_X_V 0xfc0ff07f #define MATCH_VFCVT_RTZ_XU_F_V 0x88031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f #define MATCH_VFCVT_RTZ_X_F_V 0x88039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_XU_F_V 0x88041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_X_F_V 0x88049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MASK_VFWCVT_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_F_XU_V 0x88051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f #define MATCH_VFWCVT_F_X_V 0x88059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MASK_VFWCVT_F_X_V 0xfc0ff07f #define MATCH_VFWCVT_F_F_V 0x88061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MASK_VFWCVT_F_F_V 0xfc0ff07f #define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_RTZ_X_F_V 0x88079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFNCVT_XU_F_W 0x88081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_X_F_W 0x88089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MASK_VFNCVT_X_F_W 0xfc0ff07f #define MATCH_VFNCVT_F_XU_W 0x88091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f #define MATCH_VFNCVT_F_X_W 0x88099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MASK_VFNCVT_F_X_W 0xfc0ff07f #define MATCH_VFNCVT_F_F_W 0x880a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MASK_VFNCVT_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_ROD_F_F_W 0x880a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x8c001057 -#define MASK_VFSQRT_V 0xfc0ff07f +#define MASK_VFSQRT_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x8c081057 -#define MASK_VFCLASS_V 0xfc0ff07f +#define MASK_VFCLASS_V 0xfc0ff07f #define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f +#define MASK_VFWADD_VV 0xfc00707f #define MATCH_VFWREDSUM_VS 0xc4001057 -#define MASK_VFWREDSUM_VS 0xfc00707f +#define MASK_VFWREDSUM_VS 0xfc00707f #define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f +#define MASK_VFWSUB_VV 0xfc00707f #define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MASK_VFWREDOSUM_VS 0xfc00707f #define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f +#define MASK_VFWADD_WV 0xfc00707f #define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f +#define MASK_VFWSUB_WV 0xfc00707f #define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f +#define MASK_VFWMUL_VV 0xfc00707f #define MATCH_VFDOT_VV 0xe4001057 -#define MASK_VFDOT_VV 0xfc00707f +#define MASK_VFDOT_VV 0xfc00707f #define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f +#define MASK_VFWMACC_VV 0xfc00707f #define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f +#define MASK_VFWNMACC_VV 0xfc00707f #define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f +#define MASK_VFWMSAC_VV 0xfc00707f #define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f +#define MASK_VFWNMSAC_VV 0xfc00707f #define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f +#define MASK_VADD_VX 0xfc00707f #define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f +#define MASK_VSUB_VX 0xfc00707f #define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f +#define MASK_VRSUB_VX 0xfc00707f #define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f +#define MASK_VMINU_VX 0xfc00707f #define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f +#define MASK_VMIN_VX 0xfc00707f #define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f +#define MASK_VMAXU_VX 0xfc00707f #define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f +#define MASK_VMAX_VX 0xfc00707f #define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f +#define MASK_VAND_VX 0xfc00707f #define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f +#define MASK_VOR_VX 0xfc00707f #define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f +#define MASK_VXOR_VX 0xfc00707f #define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f +#define MASK_VRGATHER_VX 0xfc00707f #define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f +#define MASK_VSLIDEUP_VX 0xfc00707f #define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MASK_VSLIDEDOWN_VX 0xfc00707f #define MATCH_VADC_VXM 0x40004057 -#define MASK_VADC_VXM 0xfe00707f +#define MASK_VADC_VXM 0xfe00707f #define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfc00707f +#define MASK_VMADC_VXM 0xfc00707f #define MATCH_VSBC_VXM 0x48004057 -#define MASK_VSBC_VXM 0xfe00707f +#define MASK_VSBC_VXM 0xfe00707f #define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfc00707f +#define MASK_VMSBC_VXM 0xfc00707f #define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f +#define MASK_VMERGE_VXM 0xfe00707f #define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f +#define MASK_VMV_V_X 0xfff0707f #define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f +#define MASK_VMSEQ_VX 0xfc00707f #define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f +#define MASK_VMSNE_VX 0xfc00707f #define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f +#define MASK_VMSLTU_VX 0xfc00707f #define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f +#define MASK_VMSLT_VX 0xfc00707f #define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f +#define MASK_VMSLEU_VX 0xfc00707f #define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f +#define MASK_VMSLE_VX 0xfc00707f #define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f +#define MASK_VMSGTU_VX 0xfc00707f #define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f +#define MASK_VMSGT_VX 0xfc00707f #define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f +#define MASK_VSADDU_VX 0xfc00707f #define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f +#define MASK_VSADD_VX 0xfc00707f #define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f +#define MASK_VSSUBU_VX 0xfc00707f #define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f +#define MASK_VSSUB_VX 0xfc00707f #define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f +#define MASK_VSLL_VX 0xfc00707f #define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f +#define MASK_VSMUL_VX 0xfc00707f #define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f +#define MASK_VSRL_VX 0xfc00707f #define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f +#define MASK_VSRA_VX 0xfc00707f #define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f +#define MASK_VSSRL_VX 0xfc00707f #define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f +#define MASK_VSSRA_VX 0xfc00707f #define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f +#define MASK_VNSRL_WX 0xfc00707f #define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f +#define MASK_VNSRA_WX 0xfc00707f #define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f +#define MASK_VNCLIPU_WX 0xfc00707f #define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f +#define MASK_VNCLIP_WX 0xfc00707f #define MATCH_VQMACCU_VX 0xf0004057 -#define MASK_VQMACCU_VX 0xfc00707f +#define MASK_VQMACCU_VX 0xfc00707f #define MATCH_VQMACC_VX 0xf4004057 -#define MASK_VQMACC_VX 0xfc00707f +#define MASK_VQMACC_VX 0xfc00707f #define MATCH_VQMACCUS_VX 0xf8004057 -#define MASK_VQMACCUS_VX 0xfc00707f +#define MASK_VQMACCUS_VX 0xfc00707f #define MATCH_VQMACCSU_VX 0xfc004057 -#define MASK_VQMACCSU_VX 0xfc00707f +#define MASK_VQMACCSU_VX 0xfc00707f #define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f +#define MASK_VADD_VV 0xfc00707f #define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f +#define MASK_VSUB_VV 0xfc00707f #define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f +#define MASK_VMINU_VV 0xfc00707f #define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f +#define MASK_VMIN_VV 0xfc00707f #define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f +#define MASK_VMAXU_VV 0xfc00707f #define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f +#define MASK_VMAX_VV 0xfc00707f #define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f +#define MASK_VAND_VV 0xfc00707f #define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f +#define MASK_VOR_VV 0xfc00707f #define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f +#define MASK_VXOR_VV 0xfc00707f #define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f +#define MASK_VRGATHER_VV 0xfc00707f #define MATCH_VADC_VVM 0x40000057 -#define MASK_VADC_VVM 0xfe00707f +#define MASK_VADC_VVM 0xfe00707f #define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfc00707f +#define MASK_VMADC_VVM 0xfc00707f #define MATCH_VSBC_VVM 0x48000057 -#define MASK_VSBC_VVM 0xfe00707f +#define MASK_VSBC_VVM 0xfe00707f #define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfc00707f +#define MASK_VMSBC_VVM 0xfc00707f #define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f +#define MASK_VMERGE_VVM 0xfe00707f #define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f +#define MASK_VMV_V_V 0xfff0707f #define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f +#define MASK_VMSEQ_VV 0xfc00707f #define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f +#define MASK_VMSNE_VV 0xfc00707f #define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f +#define MASK_VMSLTU_VV 0xfc00707f #define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f +#define MASK_VMSLT_VV 0xfc00707f #define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f +#define MASK_VMSLEU_VV 0xfc00707f #define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f +#define MASK_VMSLE_VV 0xfc00707f #define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f +#define MASK_VSADDU_VV 0xfc00707f #define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f +#define MASK_VSADD_VV 0xfc00707f #define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f +#define MASK_VSSUBU_VV 0xfc00707f #define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f +#define MASK_VSSUB_VV 0xfc00707f #define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f +#define MASK_VSLL_VV 0xfc00707f #define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f +#define MASK_VSMUL_VV 0xfc00707f #define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f +#define MASK_VSRL_VV 0xfc00707f #define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f +#define MASK_VSRA_VV 0xfc00707f #define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f +#define MASK_VSSRL_VV 0xfc00707f #define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f +#define MASK_VSSRA_VV 0xfc00707f #define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f +#define MASK_VNSRL_WV 0xfc00707f #define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f +#define MASK_VNSRA_WV 0xfc00707f #define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f +#define MASK_VNCLIPU_WV 0xfc00707f #define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f +#define MASK_VNCLIP_WV 0xfc00707f #define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f +#define MASK_VWREDSUMU_VS 0xfc00707f #define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f +#define MASK_VWREDSUM_VS 0xfc00707f #define MATCH_VDOTU_VV 0xe0000057 -#define MASK_VDOTU_VV 0xfc00707f +#define MASK_VDOTU_VV 0xfc00707f #define MATCH_VDOT_VV 0xe4000057 -#define MASK_VDOT_VV 0xfc00707f +#define MASK_VDOT_VV 0xfc00707f #define MATCH_VQMACCU_VV 0xf0000057 -#define MASK_VQMACCU_VV 0xfc00707f +#define MASK_VQMACCU_VV 0xfc00707f #define MATCH_VQMACC_VV 0xf4000057 -#define MASK_VQMACC_VV 0xfc00707f +#define MASK_VQMACC_VV 0xfc00707f #define MATCH_VQMACCSU_VV 0xfc000057 -#define MASK_VQMACCSU_VV 0xfc00707f +#define MASK_VQMACCSU_VV 0xfc00707f #define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f +#define MASK_VADD_VI 0xfc00707f #define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f +#define MASK_VRSUB_VI 0xfc00707f #define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f +#define MASK_VAND_VI 0xfc00707f #define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f +#define MASK_VOR_VI 0xfc00707f #define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f +#define MASK_VXOR_VI 0xfc00707f #define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f +#define MASK_VRGATHER_VI 0xfc00707f #define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f +#define MASK_VSLIDEUP_VI 0xfc00707f #define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MASK_VSLIDEDOWN_VI 0xfc00707f #define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f +#define MASK_VADC_VIM 0xfe00707f #define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfc00707f +#define MASK_VMADC_VIM 0xfc00707f #define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f +#define MASK_VMERGE_VIM 0xfe00707f #define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f +#define MASK_VMV_V_I 0xfff0707f #define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f +#define MASK_VMSEQ_VI 0xfc00707f #define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f +#define MASK_VMSNE_VI 0xfc00707f #define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f +#define MASK_VMSLEU_VI 0xfc00707f #define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f +#define MASK_VMSLE_VI 0xfc00707f #define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f +#define MASK_VMSGTU_VI 0xfc00707f #define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f +#define MASK_VMSGT_VI 0xfc00707f #define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f +#define MASK_VSADDU_VI 0xfc00707f #define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f +#define MASK_VSADD_VI 0xfc00707f #define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f +#define MASK_VSLL_VI 0xfc00707f #define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f +#define MASK_VMV1R_V 0xfe0ff07f #define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f +#define MASK_VMV2R_V 0xfe0ff07f #define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f +#define MASK_VMV4R_V 0xfe0ff07f #define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f +#define MASK_VMV8R_V 0xfe0ff07f #define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f +#define MASK_VSRL_VI 0xfc00707f #define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f +#define MASK_VSRA_VI 0xfc00707f #define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f +#define MASK_VSSRL_VI 0xfc00707f #define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f +#define MASK_VSSRA_VI 0xfc00707f #define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f +#define MASK_VNSRL_WI 0xfc00707f #define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f +#define MASK_VNSRA_WI 0xfc00707f #define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f +#define MASK_VNCLIPU_WI 0xfc00707f #define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f +#define MASK_VNCLIP_WI 0xfc00707f #define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f +#define MASK_VREDSUM_VS 0xfc00707f #define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f +#define MASK_VREDAND_VS 0xfc00707f #define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f +#define MASK_VREDOR_VS 0xfc00707f #define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f +#define MASK_VREDXOR_VS 0xfc00707f #define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f +#define MASK_VREDMINU_VS 0xfc00707f #define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f +#define MASK_VREDMIN_VS 0xfc00707f #define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f +#define MASK_VREDMAXU_VS 0xfc00707f #define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f +#define MASK_VREDMAX_VS 0xfc00707f #define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f +#define MASK_VAADDU_VV 0xfc00707f #define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f +#define MASK_VAADD_VV 0xfc00707f #define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f +#define MASK_VASUBU_VV 0xfc00707f #define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f +#define MASK_VASUB_VV 0xfc00707f #define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f +#define MASK_VMV_X_S 0xfe0ff07f #define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f +#define MASK_VCOMPRESS_VM 0xfe00707f #define MATCH_VMANDNOT_MM 0x60002057 -#define MASK_VMANDNOT_MM 0xfc00707f +#define MASK_VMANDNOT_MM 0xfc00707f #define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f +#define MASK_VMAND_MM 0xfc00707f #define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f +#define MASK_VMOR_MM 0xfc00707f #define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f +#define MASK_VMXOR_MM 0xfc00707f #define MATCH_VMORNOT_MM 0x70002057 -#define MASK_VMORNOT_MM 0xfc00707f +#define MASK_VMORNOT_MM 0xfc00707f #define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f +#define MASK_VMNAND_MM 0xfc00707f #define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f +#define MASK_VMNOR_MM 0xfc00707f #define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f +#define MASK_VMXNOR_MM 0xfc00707f #define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f +#define MASK_VMSBF_M 0xfc0ff07f #define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f +#define MASK_VMSOF_M 0xfc0ff07f #define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f +#define MASK_VMSIF_M 0xfc0ff07f #define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f +#define MASK_VIOTA_M 0xfc0ff07f #define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f +#define MASK_VID_V 0xfdfff07f #define MATCH_VPOPC_M 0x40082057 -#define MASK_VPOPC_M 0xfc0ff07f +#define MASK_VPOPC_M 0xfc0ff07f #define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f +#define MASK_VFIRST_M 0xfc0ff07f #define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f +#define MASK_VDIVU_VV 0xfc00707f #define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f +#define MASK_VDIV_VV 0xfc00707f #define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f +#define MASK_VREMU_VV 0xfc00707f #define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f +#define MASK_VREM_VV 0xfc00707f #define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f +#define MASK_VMULHU_VV 0xfc00707f #define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f +#define MASK_VMUL_VV 0xfc00707f #define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f +#define MASK_VMULHSU_VV 0xfc00707f #define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f +#define MASK_VMULH_VV 0xfc00707f #define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f +#define MASK_VMADD_VV 0xfc00707f #define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f +#define MASK_VNMSUB_VV 0xfc00707f #define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f +#define MASK_VMACC_VV 0xfc00707f #define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f +#define MASK_VNMSAC_VV 0xfc00707f #define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f +#define MASK_VWADDU_VV 0xfc00707f #define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f +#define MASK_VWADD_VV 0xfc00707f #define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f +#define MASK_VWSUBU_VV 0xfc00707f #define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f +#define MASK_VWSUB_VV 0xfc00707f #define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f +#define MASK_VWADDU_WV 0xfc00707f #define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f +#define MASK_VWADD_WV 0xfc00707f #define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f +#define MASK_VWSUBU_WV 0xfc00707f #define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f +#define MASK_VWSUB_WV 0xfc00707f #define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f +#define MASK_VWMULU_VV 0xfc00707f #define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f +#define MASK_VWMULSU_VV 0xfc00707f #define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f +#define MASK_VWMUL_VV 0xfc00707f #define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f +#define MASK_VWMACCU_VV 0xfc00707f #define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f +#define MASK_VWMACC_VV 0xfc00707f #define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f +#define MASK_VWMACCSU_VV 0xfc00707f #define MATCH_VAADDU_VX 0x20006057 -#define MASK_VAADDU_VX 0xfc00707f +#define MASK_VAADDU_VX 0xfc00707f #define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f +#define MASK_VAADD_VX 0xfc00707f #define MATCH_VASUBU_VX 0x28006057 -#define MASK_VASUBU_VX 0xfc00707f +#define MASK_VASUBU_VX 0xfc00707f #define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f +#define MASK_VASUB_VX 0xfc00707f #define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f +#define MASK_VMV_S_X 0xfff0707f #define MATCH_VSLIDE1UP_VX 0x38006057 -#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MASK_VSLIDE1UP_VX 0xfc00707f #define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MASK_VSLIDE1DOWN_VX 0xfc00707f #define MATCH_VDIVU_VX 0x80006057 -#define MASK_VDIVU_VX 0xfc00707f +#define MASK_VDIVU_VX 0xfc00707f #define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f +#define MASK_VDIV_VX 0xfc00707f #define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f +#define MASK_VREMU_VX 0xfc00707f #define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f +#define MASK_VREM_VX 0xfc00707f #define MATCH_VMULHU_VX 0x90006057 -#define MASK_VMULHU_VX 0xfc00707f +#define MASK_VMULHU_VX 0xfc00707f #define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f +#define MASK_VMUL_VX 0xfc00707f #define MATCH_VMULHSU_VX 0x98006057 -#define MASK_VMULHSU_VX 0xfc00707f +#define MASK_VMULHSU_VX 0xfc00707f #define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f +#define MASK_VMULH_VX 0xfc00707f #define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f +#define MASK_VMADD_VX 0xfc00707f #define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f +#define MASK_VNMSUB_VX 0xfc00707f #define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f +#define MASK_VMACC_VX 0xfc00707f #define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f +#define MASK_VNMSAC_VX 0xfc00707f #define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f +#define MASK_VWADDU_VX 0xfc00707f #define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f +#define MASK_VWADD_VX 0xfc00707f #define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f +#define MASK_VWSUBU_VX 0xfc00707f #define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f +#define MASK_VWSUB_VX 0xfc00707f #define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f +#define MASK_VWADDU_WX 0xfc00707f #define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f +#define MASK_VWADD_WX 0xfc00707f #define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f +#define MASK_VWSUBU_WX 0xfc00707f #define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f +#define MASK_VWSUB_WX 0xfc00707f #define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f +#define MASK_VWMULU_VX 0xfc00707f #define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f +#define MASK_VWMULSU_VX 0xfc00707f #define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f +#define MASK_VWMUL_VX 0xfc00707f #define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f +#define MASK_VWMACCU_VX 0xfc00707f #define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f +#define MASK_VWMACC_VX 0xfc00707f #define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f +#define MASK_VWMACCUS_VX 0xfc00707f #define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f +#define MASK_VWMACCSU_VX 0xfc00707f #define MATCH_VAMOSWAPW_V 0x800602f -#define MASK_VAMOSWAPW_V 0xf800707f +#define MASK_VAMOSWAPW_V 0xf800707f #define MATCH_VAMOADDW_V 0x602f -#define MASK_VAMOADDW_V 0xf800707f +#define MASK_VAMOADDW_V 0xf800707f #define MATCH_VAMOXORW_V 0x2000602f -#define MASK_VAMOXORW_V 0xf800707f +#define MASK_VAMOXORW_V 0xf800707f #define MATCH_VAMOANDW_V 0x6000602f -#define MASK_VAMOANDW_V 0xf800707f +#define MASK_VAMOANDW_V 0xf800707f #define MATCH_VAMOORW_V 0x4000602f -#define MASK_VAMOORW_V 0xf800707f +#define MASK_VAMOORW_V 0xf800707f #define MATCH_VAMOMINW_V 0x8000602f -#define MASK_VAMOMINW_V 0xf800707f +#define MASK_VAMOMINW_V 0xf800707f #define MATCH_VAMOMAXW_V 0xa000602f -#define MASK_VAMOMAXW_V 0xf800707f +#define MASK_VAMOMAXW_V 0xf800707f #define MATCH_VAMOMINUW_V 0xc000602f -#define MASK_VAMOMINUW_V 0xf800707f +#define MASK_VAMOMINUW_V 0xf800707f #define MATCH_VAMOMAXUW_V 0xe000602f -#define MASK_VAMOMAXUW_V 0xf800707f +#define MASK_VAMOMAXUW_V 0xf800707f #define MATCH_VAMOSWAPE_V 0x800702f -#define MASK_VAMOSWAPE_V 0xf800707f +#define MASK_VAMOSWAPE_V 0xf800707f #define MATCH_VAMOADDE_V 0x702f -#define MASK_VAMOADDE_V 0xf800707f +#define MASK_VAMOADDE_V 0xf800707f #define MATCH_VAMOXORE_V 0x2000702f -#define MASK_VAMOXORE_V 0xf800707f +#define MASK_VAMOXORE_V 0xf800707f #define MATCH_VAMOANDE_V 0x6000702f -#define MASK_VAMOANDE_V 0xf800707f +#define MASK_VAMOANDE_V 0xf800707f #define MATCH_VAMOORE_V 0x4000702f -#define MASK_VAMOORE_V 0xf800707f +#define MASK_VAMOORE_V 0xf800707f #define MATCH_VAMOMINE_V 0x8000702f -#define MASK_VAMOMINE_V 0xf800707f +#define MASK_VAMOMINE_V 0xf800707f #define MATCH_VAMOMAXE_V 0xa000702f -#define MASK_VAMOMAXE_V 0xf800707f +#define MASK_VAMOMAXE_V 0xf800707f #define MATCH_VAMOMINUE_V 0xc000702f -#define MASK_VAMOMINUE_V 0xf800707f +#define MASK_VAMOMINUE_V 0xf800707f #define MATCH_VAMOMAXUE_V 0xe000702f -#define MASK_VAMOMAXUE_V 0xf800707f +#define MASK_VAMOMAXUE_V 0xf800707f #define MATCH_VMVNFR_V 0x9e003057 -#define MASK_VMVNFR_V 0xfe00707f +#define MASK_VMVNFR_V 0xfe00707f #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 @@ -2183,29 +2143,25 @@ DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, - MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, - MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, - MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, - MASK_CUSTOM3_RD_RS1_RS2) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) DECLARE_INSN(vlb_v, MATCH_VLB_V, MASK_VLB_V) diff --git a/vendor/riscv-test-env/p/link.ld b/vendor/riscv-test-env/p/link.ld new file mode 100644 index 00000000..b3e315e7 --- /dev/null +++ b/vendor/riscv-test-env/p/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/dv/uvm/core_ibex/directed_tests/riscv_test.h b/vendor/riscv-test-env/p/riscv_test.h similarity index 99% rename from dv/uvm/core_ibex/directed_tests/riscv_test.h rename to vendor/riscv-test-env/p/riscv_test.h index 6ce12a4e..18fdc0a7 100644 --- a/dv/uvm/core_ibex/directed_tests/riscv_test.h +++ b/vendor/riscv-test-env/p/riscv_test.h @@ -5,6 +5,7 @@ #define _ENV_PHYSICAL_SINGLE_CORE_H #include "encoding.h" +#include "ibex_macros.h" //----------------------------------------------------------------------- // Begin Macro diff --git a/vendor/riscv-test-env/pm/link.ld b/vendor/riscv-test-env/pm/link.ld new file mode 100644 index 00000000..b3e315e7 --- /dev/null +++ b/vendor/riscv-test-env/pm/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/vendor/riscv-test-env/pm/riscv_test.h b/vendor/riscv-test-env/pm/riscv_test.h new file mode 100644 index 00000000..38a0e86b --- /dev/null +++ b/vendor/riscv-test-env/pm/riscv_test.h @@ -0,0 +1,11 @@ +// See LICENSE for license details. + +#ifndef _ENV_PHYSICAL_MULTI_CORE_H +#define _ENV_PHYSICAL_MULTI_CORE_H + +#include "../p/riscv_test.h" + +#undef RISCV_MULTICORE_DISABLE +#define RISCV_MULTICORE_DISABLE + +#endif diff --git a/vendor/riscv-test-env/pt/link.ld b/vendor/riscv-test-env/pt/link.ld new file mode 100644 index 00000000..b3e315e7 --- /dev/null +++ b/vendor/riscv-test-env/pt/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/vendor/riscv-test-env/pt/riscv_test.h b/vendor/riscv-test-env/pt/riscv_test.h new file mode 100644 index 00000000..34c2a331 --- /dev/null +++ b/vendor/riscv-test-env/pt/riscv_test.h @@ -0,0 +1,69 @@ +// See LICENSE for license details. + +#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H +#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H + +#include "../p/riscv_test.h" + +#define TIMER_INTERVAL 2 + +#undef EXTRA_INIT_TIMER +#define EXTRA_INIT_TIMER \ + li a0, MIP_MTIP; \ + csrs mie, a0; \ + csrr a0, mtime; \ + addi a0, a0, TIMER_INTERVAL; \ + csrw mtimecmp, a0; \ + +#if SSTATUS_XS != 0x18000 +# error +#endif +#define XS_SHIFT 15 + +#undef INTERRUPT_HANDLER +#define INTERRUPT_HANDLER \ + slli t5, t5, 1; \ + srli t5, t5, 1; \ + add t5, t5, -IRQ_M_TIMER; \ + bnez t5, other_exception; /* other interrups shouldn't happen */\ + csrr t5, mtime; \ + addi t5, t5, TIMER_INTERVAL; \ + csrw mtimecmp, t5; \ + mret; \ + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#undef EXTRA_DATA +#define EXTRA_DATA \ + .align 3; \ +regspill: \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ +evac: \ + .skip 32768; \ + +#endif diff --git a/vendor/riscv-test-env/v/entry.S b/vendor/riscv-test-env/v/entry.S new file mode 100644 index 00000000..49b2d3ed --- /dev/null +++ b/vendor/riscv-test-env/v/entry.S @@ -0,0 +1,162 @@ +#include "riscv_test.h" + +#if __riscv_xlen == 64 +# define STORE sd +# define LOAD ld +# define REGBYTES 8 +#else +# define STORE sw +# define LOAD lw +# define REGBYTES 4 +#endif + +#define STACK_TOP (_end + 4096) + + .section ".text.init","ax",@progbits + .globl _start + .align 2 +_start: + j handle_reset + + /* NMI vector */ + .align 2 +nmi_vector: + j wtf + + .align 2 +trap_vector: + j wtf + +handle_reset: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + la t0, trap_vector + csrw mtvec, t0 + la sp, STACK_TOP - SIZEOF_TRAPFRAME_T + csrr t0, mhartid + slli t0, t0, 12 + add sp, sp, t0 + csrw mscratch, sp + call extra_boot + la a0, userstart + j vm_boot + + .globl pop_tf +pop_tf: + LOAD t0,33*REGBYTES(a0) + csrw sepc,t0 + LOAD x1,1*REGBYTES(a0) + LOAD x2,2*REGBYTES(a0) + LOAD x3,3*REGBYTES(a0) + LOAD x4,4*REGBYTES(a0) + LOAD x5,5*REGBYTES(a0) + LOAD x6,6*REGBYTES(a0) + LOAD x7,7*REGBYTES(a0) + LOAD x8,8*REGBYTES(a0) + LOAD x9,9*REGBYTES(a0) + LOAD x11,11*REGBYTES(a0) + LOAD x12,12*REGBYTES(a0) + LOAD x13,13*REGBYTES(a0) + LOAD x14,14*REGBYTES(a0) + LOAD x15,15*REGBYTES(a0) + LOAD x16,16*REGBYTES(a0) + LOAD x17,17*REGBYTES(a0) + LOAD x18,18*REGBYTES(a0) + LOAD x19,19*REGBYTES(a0) + LOAD x20,20*REGBYTES(a0) + LOAD x21,21*REGBYTES(a0) + LOAD x22,22*REGBYTES(a0) + LOAD x23,23*REGBYTES(a0) + LOAD x24,24*REGBYTES(a0) + LOAD x25,25*REGBYTES(a0) + LOAD x26,26*REGBYTES(a0) + LOAD x27,27*REGBYTES(a0) + LOAD x28,28*REGBYTES(a0) + LOAD x29,29*REGBYTES(a0) + LOAD x30,30*REGBYTES(a0) + LOAD x31,31*REGBYTES(a0) + LOAD a0,10*REGBYTES(a0) + sret + + .global trap_entry + .align 2 +trap_entry: + csrrw sp, sscratch, sp + + # save gprs + STORE x1,1*REGBYTES(sp) + STORE x3,3*REGBYTES(sp) + STORE x4,4*REGBYTES(sp) + STORE x5,5*REGBYTES(sp) + STORE x6,6*REGBYTES(sp) + STORE x7,7*REGBYTES(sp) + STORE x8,8*REGBYTES(sp) + STORE x9,9*REGBYTES(sp) + STORE x10,10*REGBYTES(sp) + STORE x11,11*REGBYTES(sp) + STORE x12,12*REGBYTES(sp) + STORE x13,13*REGBYTES(sp) + STORE x14,14*REGBYTES(sp) + STORE x15,15*REGBYTES(sp) + STORE x16,16*REGBYTES(sp) + STORE x17,17*REGBYTES(sp) + STORE x18,18*REGBYTES(sp) + STORE x19,19*REGBYTES(sp) + STORE x20,20*REGBYTES(sp) + STORE x21,21*REGBYTES(sp) + STORE x22,22*REGBYTES(sp) + STORE x23,23*REGBYTES(sp) + STORE x24,24*REGBYTES(sp) + STORE x25,25*REGBYTES(sp) + STORE x26,26*REGBYTES(sp) + STORE x27,27*REGBYTES(sp) + STORE x28,28*REGBYTES(sp) + STORE x29,29*REGBYTES(sp) + STORE x30,30*REGBYTES(sp) + STORE x31,31*REGBYTES(sp) + + csrrw t0,sscratch,sp + STORE t0,2*REGBYTES(sp) + + # get sr, epc, badvaddr, cause + csrr t0,sstatus + STORE t0,32*REGBYTES(sp) + csrr t0,sepc + STORE t0,33*REGBYTES(sp) + csrr t0,stval + STORE t0,34*REGBYTES(sp) + csrr t0,scause + STORE t0,35*REGBYTES(sp) + + move a0, sp + j handle_trap diff --git a/vendor/riscv-test-env/v/link.ld b/vendor/riscv-test-env/v/link.ld new file mode 100644 index 00000000..b3e315e7 --- /dev/null +++ b/vendor/riscv-test-env/v/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/vendor/riscv-test-env/v/riscv_test.h b/vendor/riscv-test-env/v/riscv_test.h new file mode 100644 index 00000000..c74e05d1 --- /dev/null +++ b/vendor/riscv-test-env/v/riscv_test.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _ENV_VIRTUAL_SINGLE_CORE_H +#define _ENV_VIRTUAL_SINGLE_CORE_H + +#include "../p/riscv_test.h" + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#undef RVTEST_FP_ENABLE +#define RVTEST_FP_ENABLE fssr x0 + +#undef RVTEST_VECTOR_ENABLE +#define RVTEST_VECTOR_ENABLE \ + csrwi fcsr, 0; \ + csrwi vcsr, 0; + +#undef RVTEST_CODE_BEGIN +#define RVTEST_CODE_BEGIN \ + .text; \ + .global extra_boot; \ +extra_boot: \ + EXTRA_INIT \ + ret; \ + .global userstart; \ +userstart: \ + init + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- + +#undef RVTEST_PASS +#define RVTEST_PASS li a0, 1; scall + +#undef RVTEST_FAIL +#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall; + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#undef RVTEST_DATA_END +#define RVTEST_DATA_END + +//----------------------------------------------------------------------- +// Supervisor mode definitions and macros +//----------------------------------------------------------------------- + +#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below +#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1)) + +#define PGSHIFT 12 +#define PGSIZE (1UL << PGSHIFT) + +#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36) + +#ifndef __ASSEMBLER__ + +typedef unsigned long pte_t; +#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2) +#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2)) +#define VPN_BITS (PTIDXBITS * LEVELS) +#define VA_BITS (VPN_BITS + PGSHIFT) +#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS) +#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE) + +typedef struct +{ + long gpr[32]; + long sr; + long epc; + long badvaddr; + long cause; +} trapframe_t; +#endif + +#endif diff --git a/vendor/riscv-test-env/v/string.c b/vendor/riscv-test-env/v/string.c new file mode 100644 index 00000000..4ffedc0a --- /dev/null +++ b/vendor/riscv-test-env/v/string.c @@ -0,0 +1,114 @@ +#include +#include +#include + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +int memcmp(const void* s1, const void* s2, size_t n) +{ + if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* u1 = s1; + const uintptr_t* u2 = s2; + const uintptr_t* end = u1 + (n / sizeof(uintptr_t)); + while (u1 < end) { + if (*u1 != *u2) + break; + u1++; + u2++; + } + n -= (const void*)u1 - s1; + s1 = u1; + s2 = u2; + } + + while (n--) { + unsigned char c1 = *(const unsigned char*)s1++; + unsigned char c2 = *(const unsigned char*)s2++; + if (c1 != c2) + return c1 - c2; + } + + return 0; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} diff --git a/vendor/riscv-test-env/v/vm.c b/vendor/riscv-test-env/v/vm.c new file mode 100644 index 00000000..277b67c6 --- /dev/null +++ b/vendor/riscv-test-env/v/vm.c @@ -0,0 +1,300 @@ +// See LICENSE for license details. + +#include +#include +#include + +#include "riscv_test.h" + +#if __riscv_xlen == 32 +# define SATP_MODE_CHOICE SATP_MODE_SV32 +#elif defined(Sv48) +# define SATP_MODE_CHOICE SATP_MODE_SV48 +#else +# define SATP_MODE_CHOICE SATP_MODE_SV39 +#endif + +void trap_entry(); +void pop_tf(trapframe_t*); + +extern volatile uint64_t tohost; +extern volatile uint64_t fromhost; + +static void do_tohost(uint64_t tohost_value) +{ + while (tohost) + fromhost = 0; + tohost = tohost_value; +} + +#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE) +#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) + +#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory") + +static uint64_t lfsr63(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + return (x >> 1) | (bit << 62); +} + +static void cputchar(int x) +{ + do_tohost(0x0101000000000000 | (unsigned char)x); +} + +static void cputstring(const char* s) +{ + while (*s) + cputchar(*s++); +} + +static void terminate(int code) +{ + do_tohost(code); + while (1); +} + +void wtf() +{ + terminate(841); +} + +#define stringify1(x) #x +#define stringify(x) stringify1(x) +#define assert(x) do { \ + if (x) break; \ + cputstring("Assertion failed: " stringify(x) "\n"); \ + terminate(3); \ +} while(0) + +#define l1pt pt[0] +#define user_l2pt pt[1] +#if SATP_MODE_CHOICE == SATP_MODE_SV48 +# define NPT 6 +# define kernel_l2pt pt[2] +# define kernel_l3pt pt[3] +# define user_l3pt pt[4] +# define user_llpt pt[5] +#elif SATP_MODE_CHOICE == SATP_MODE_SV39 +# define NPT 4 +# define kernel_l2pt pt[2] +# define user_llpt pt[3] +#elif SATP_MODE_CHOICE == SATP_MODE_SV32 +# define NPT 2 +# define user_llpt user_l2pt +#else +# error Unknown SATP_MODE_CHOICE +#endif +pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE))); + +typedef struct { pte_t addr; void* next; } freelist_t; + +freelist_t user_mapping[MAX_TEST_PAGES]; +freelist_t freelist_nodes[MAX_TEST_PAGES]; +freelist_t *freelist_head, *freelist_tail; + +void printhex(uint64_t x) +{ + char str[17]; + for (int i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + cputstring(str); +} + +static void evict(unsigned long addr) +{ + assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); + addr = addr/PGSIZE*PGSIZE; + + freelist_t* node = &user_mapping[addr/PGSIZE]; + if (node->addr) + { + // check accessed and dirty bits + assert(user_llpt[addr/PGSIZE] & PTE_A); + uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); + if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { + assert(user_llpt[addr/PGSIZE] & PTE_D); + memcpy(uva2kva(addr), (void*)addr, PGSIZE); + } + write_csr(sstatus, sstatus); + + user_mapping[addr/PGSIZE].addr = 0; + + if (freelist_tail == 0) + freelist_head = freelist_tail = node; + else + { + freelist_tail->next = node; + freelist_tail = node; + } + } +} + +void handle_fault(uintptr_t addr, uintptr_t cause) +{ + assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); + addr = addr/PGSIZE*PGSIZE; + + if (user_llpt[addr/PGSIZE]) { + if (!(user_llpt[addr/PGSIZE] & PTE_A)) { + user_llpt[addr/PGSIZE] |= PTE_A; + } else { + assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); + user_llpt[addr/PGSIZE] |= PTE_D; + } + flush_page(addr); + return; + } + + freelist_t* node = freelist_head; + assert(node); + freelist_head = node->next; + if (freelist_head == freelist_tail) + freelist_tail = 0; + + uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X; + user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D; + flush_page(addr); + + assert(user_mapping[addr/PGSIZE].addr == 0); + user_mapping[addr/PGSIZE] = *node; + + uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); + memcpy((void*)addr, uva2kva(addr), PGSIZE); + write_csr(sstatus, sstatus); + + user_llpt[addr/PGSIZE] = new_pte; + flush_page(addr); + + asm volatile ("fence.i"); +} + +void handle_trap(trapframe_t* tf) +{ + if (tf->cause == CAUSE_USER_ECALL) + { + int n = tf->gpr[10]; + + for (long i = 1; i < MAX_TEST_PAGES; i++) + evict(i*PGSIZE); + + terminate(n); + } + else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) + { + assert(tf->epc % 4 == 0); + + int* fssr; + asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr)); + + if (*(int*)tf->epc == *fssr) + terminate(1); // FP test on non-FP hardware. "succeed." + else + assert(!"illegal instruction"); + tf->epc += 4; + } + else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) + handle_fault(tf->badvaddr, tf->cause); + else + assert(!"unexpected exception"); + + pop_tf(tf); +} + +static void coherence_torture() +{ + // cause coherence misses without affecting program semantics + uint64_t random = ENTROPY; + while (1) { + uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); +#ifdef __riscv_atomic + if (random & 1) // perform a no-op write + asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr)); + else // perform a read +#endif + asm volatile ("lw zero, (%0)" :: "r"(paddr)); + random = lfsr63(random); + } +} + +void vm_boot(uintptr_t test_addr) +{ + uint64_t random = ENTROPY; + if (read_csr(mhartid) > 0) + coherence_torture(); + + _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???"); + +#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0 +# error +#endif + // map user to lowermost megapage + l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + // map kernel to uppermost megapage +#if SATP_MODE_CHOICE == SATP_MODE_SV48 + l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + kernel_l3pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; + user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; +#elif SATP_MODE_CHOICE == SATP_MODE_SV39 + l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; + user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; +#elif SATP_MODE_CHOICE == SATP_MODE_SV32 + l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; +#else +# error +#endif + uintptr_t vm_choice = SATP_MODE_CHOICE; + uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT) + | (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))); + write_csr(satp, satp_value); + if (read_csr(satp) != satp_value) + assert(!"unsupported satp mode"); + + // Set up PMPs if present, ignoring illegal instruction trap if not. + uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1; + asm volatile ("la t0, 1f\n\t" + "csrrw t0, mtvec, t0\n\t" + "csrw pmpaddr0, %1\n\t" + "csrw pmpcfg0, %0\n\t" + ".align 2\n\t" + "1: csrw mtvec, t0" + : : "r" (pmpc), "r" (pmpa) : "t0"); + + // set up supervisor trap handling + write_csr(stvec, pa2kva(trap_entry)); + write_csr(sscratch, pa2kva(read_csr(mscratch))); + write_csr(medeleg, + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT)); + // FPU on; accelerator on; vector unit on + write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS); + write_csr(mie, 0); + + random = 1 + (random % MAX_TEST_PAGES); + freelist_head = pa2kva((void*)&freelist_nodes[0]); + freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]); + for (long i = 0; i < MAX_TEST_PAGES; i++) + { + freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE; + freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); + random = LFSR_NEXT(random); + } + freelist_nodes[MAX_TEST_PAGES-1].next = 0; + + trapframe_t tf; + memset(&tf, 0, sizeof(tf)); + tf.epc = test_addr - DRAM_BASE; + pop_tf(&tf); +} diff --git a/vendor/riscv_test_env.lock.hjson b/vendor/riscv_test_env.lock.hjson new file mode 100644 index 00000000..0dff8ce8 --- /dev/null +++ b/vendor/riscv_test_env.lock.hjson @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is generated by the util/vendor script. Please do not modify it +// manually. + +{ + upstream: + { + url: https://github.com/riscv/riscv-test-env + rev: 34a1175291f9531e85afdb89aaa77707f45fc8e4 + } + patch_dir: "patches/riscv_test_env" +} diff --git a/vendor/riscv_test_env.vendor.hjson b/vendor/riscv_test_env.vendor.hjson new file mode 100644 index 00000000..474b8529 --- /dev/null +++ b/vendor/riscv_test_env.vendor.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "riscv-test-env", + target_dir: "riscv-test-env", + + upstream: { + url: "https://github.com/riscv/riscv-test-env", + rev: "master", + }, +}