From 7419ef41c36282d8d68d59a3c1e57b4cec500d09 Mon Sep 17 00:00:00 2001
From: Pasquale Davide Schiavone <pschiavo@larain4.ee.ethz.ch>
Date: Fri, 28 Sep 2018 10:45:23 +0200
Subject: [PATCH] update README

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 3853906d..2a961c6f 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,7 @@
 
 *zero-riscy** is a small 2-stage RISC-V core derived from RI5CY.
 
-**zero-riscy** fully implements the RV32IMC instruction set and a minimal 
+**zero-riscy** fully implements the RV32IMC instruction set and a minimal
 set of RISCV privileged specifications.
 **zero-riscy** can be configured to be very small by disabling the RV32M extensions
 and by activating the RV32E extensios. This configuration is called **micro-riscy**
@@ -14,5 +14,5 @@ PULP and PULPino.
 ## Documentation
 
 A datasheet that explains the most important features of the core can be found
-in  the `zeroriscy-doc` repository.
+in  the doc folder.