diff --git a/alu.sv b/alu.sv index 4966e272..e435138a 100644 --- a/alu.sv +++ b/alu.sv @@ -40,9 +40,9 @@ module alu ); - logic [31:0] operand_a_rev; // bit reversed signal of operand_a_i + logic [31:0] operand_a_rev; - // bit reverse operand_a for left shifts + // bit reverse operand_a for left shifts and bit counting genvar k; generate for(k = 0; k < 32; k++) diff --git a/id_stage.sv b/id_stage.sv index 800237ec..2a9de3f8 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -815,7 +815,7 @@ module id_stage alu_operand_b_ex_o <= 32'h0000_0000; alu_operand_c_ex_o <= 32'h0000_0000; - vector_mode_ex_o <= `VEC_MODE32; + vector_mode_ex_o <= '0; mult_en_ex_o <= 1'b0; mult_sel_subword_ex_o <= 2'b0; diff --git a/include/defines.sv b/include/defines.sv index 871017d2..2ec59260 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -29,6 +29,8 @@ `ifndef _CORE_DEFINES `define _CORE_DEFINES +`define TRACE_EXECUTION + //////////////////////////////////////////////// // ___ ____ _ // @@ -74,16 +76,6 @@ `define INSTR_BGE { 17'b?, 3'b101, 5'b?, `OPCODE_BRANCH } `define INSTR_BLTU { 17'b?, 3'b110, 5'b?, `OPCODE_BRANCH } `define INSTR_BGEU { 17'b?, 3'b111, 5'b?, `OPCODE_BRANCH } -// LOAD -`define INSTR_LB { 17'b?, 3'b000, 5'b?, `OPCODE_LOAD } -`define INSTR_LH { 17'b?, 3'b001, 5'b?, `OPCODE_LOAD } -`define INSTR_LW { 17'b?, 3'b010, 5'b?, `OPCODE_LOAD } -`define INSTR_LBU { 17'b?, 3'b100, 5'b?, `OPCODE_LOAD } -`define INSTR_LHU { 17'b?, 3'b101, 5'b?, `OPCODE_LOAD } -// STORE -`define INSTR_SB { 17'b?, 3'b000, 5'b?, `OPCODE_STORE } -`define INSTR_SH { 17'b?, 3'b001, 5'b?, `OPCODE_STORE } -`define INSTR_SW { 17'b?, 3'b010, 5'b?, `OPCODE_STORE } // OPIMM `define INSTR_ADDI { 17'b?, 3'b000, 5'b?, `OPCODE_OPIMM } `define INSTR_SLTI { 17'b?, 3'b010, 5'b?, `OPCODE_OPIMM } @@ -119,12 +111,6 @@ `define INSTR_EBREAK { 12'b000000000001, 13'b0, `OPCODE_SYSTEM } `define INSTR_ERET { 12'b000100000000, 13'b0, `OPCODE_SYSTEM } `define INSTR_WFI { 12'b000100000010, 13'b0, `OPCODE_SYSTEM } -`define INSTR_RDCYCLE { 5'b11000, 5'b0, 2'b00, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } -`define INSTR_RDCYCLEH { 5'b11001, 5'b0, 2'b00, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } -`define INSTR_RDTIME { 5'b11000, 5'b0, 2'b01, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } -`define INSTR_RDTIMEH { 5'b11001, 5'b0, 2'b01, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } -`define INSTR_RDINSTRET { 5'b11000, 5'b0, 2'b10, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } -`define INSTR_RDINSTRETH { 5'b11001, 5'b0, 2'b10, 5'b0, 3'b010, 5'b?, `OPCODE_SYSTEM } // RV32M `define INSTR_MUL { 7'b0000001, 10'b?, 3'b000, 5'b?, `OPCODE_OP } @@ -157,35 +143,37 @@ `define ALU_OP_WIDTH 6 -// Standard Operations +// No operation +`define ALU_NOP 6'b011111 + +// Standard arithmetic operations `define ALU_ADD 6'b000_000 `define ALU_SUB 6'b000_010 -`define ALU_AND 6'b000_011 -`define ALU_OR 6'b000_100 `define ALU_XOR 6'b000_101 +`define ALU_OR 6'b000_100 +`define ALU_AND 6'b000_011 -`define ALU_AVG 6'b000_110 -`define ALU_AVGU 6'b000_111 -// Shift Operations -`define ALU_SLL 6'b0010_00 -`define ALU_SRL 6'b0010_01 -`define ALU_SRA 6'b0010_10 -`define ALU_ROR 6'b0010_11 -// Set Lower Than Operations +// Set Lower Than operations `define ALU_SLTS 6'b0011_00 `define ALU_SLTU 6'b0011_01 `define ALU_SLETS 6'b0011_10 `define ALU_SLETU 6'b0011_11 -// Extension Operations + +// Shifts +`define ALU_SLL 6'b0010_00 +`define ALU_SRL 6'b0010_01 +`define ALU_SRA 6'b0010_10 +`define ALU_ROR 6'b0010_11 + +// Sign-/zero-extensions `define ALU_EXTHS 6'b010_000 `define ALU_EXTWS 6'b010_001 `define ALU_EXTBS 6'b010_010 `define ALU_EXTWZ 6'b010_011 `define ALU_EXTHZ 6'b010_100 `define ALU_EXTBZ 6'b010_110 -// No Operation -`define ALU_NOP 6'b011111 -// Comparison Operations + +// Comparisons `define ALU_EQ 6'b10_0000 `define ALU_NE 6'b10_0001 `define ALU_GTU 6'b10_0010 @@ -197,26 +185,24 @@ `define ALU_LTS 6'b10_1100 `define ALU_LES 6'b10_1101 +// Min/max/avg +`define ALU_AVG 6'b000_110 +`define ALU_AVGU 6'b000_111 `define ALU_MIN 6'b10_1110 `define ALU_MINU 6'b11_1110 `define ALU_MAX 6'b10_1111 `define ALU_MAXU 6'b11_1111 +// Absolute value `define ALU_ABS 6'b11_1010 +// Bit counting `define ALU_CNT 6'b11_0000 `define ALU_FF1 6'b11_0010 `define ALU_FL1 6'b11_0011 `define ALU_CLB 6'b11_0001 -// Vector Mode -`define VEC_MODE32 2'b00 -`define VEC_MODE16 2'b10 -`define VEC_MODE8 2'b11 -`define VEC_MODE216 2'b01 - - ///////////////////////////////////////////////////////// // ____ ____ ____ _ _ // // / ___/ ___| | _ \ ___ __ _(_)___| |_ ___ _ __ // @@ -239,9 +225,6 @@ `define CSR_OP_CLEAR 2'b11 -// SPR for HWLoops -`define SP_GRP_HWLP 5'h0C - // SPR for debugger, not accessible by CPU `define SP_DVR0 16'h3000 `define SP_DCR0 16'h3008 @@ -362,6 +345,4 @@ `define DSR_INTE 1 -//`define BRANCH_PREDICTION - `endif diff --git a/riscv_core.sv b/riscv_core.sv index ffd9905b..45b19332 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -755,12 +755,6 @@ module riscv_core `INSTR_EBREAK: printMnemonic("EBREAK"); `INSTR_ERET: printMnemonic("ERET"); `INSTR_WFI: printMnemonic("WFI"); - `INSTR_RDCYCLE: printRDInstr("RDCYCLE"); - `INSTR_RDCYCLEH: printRDInstr("RDCYCLEH"); - `INSTR_RDTIME: printRDInstr("RDTIME"); - `INSTR_RDTIMEH: printRDInstr("RDTIMEH"); - `INSTR_RDINSTRET: printRDInstr("RDINSTRET"); - `INSTR_RDINSTRETH: printRDInstr("RDINSTRETH"); // RV32M `INSTR_MUL: printRInstr("MUL"); `INSTR_MULH: printRInstr("MULH"); @@ -842,13 +836,6 @@ module riscv_core end endfunction // printUJInstr - function void printRDInstr(input string mnemonic); - begin - riscv_core.mnemonic = mnemonic; - $fdisplay(f, "%7s\tx%0d", mnemonic, rd); - end - endfunction // printRDInstr - function void printCSRInstr(input string mnemonic); logic [11:0] csr; begin @@ -993,7 +980,4 @@ module riscv_core // synopsys translate_on `endif - -/////////////////// -endmodule // cpu // -/////////////////// +endmodule