diff --git a/controller.sv b/controller.sv
index 59da0286..16ffbbcf 100644
--- a/controller.sv
+++ b/controller.sv
@@ -165,7 +165,7 @@ module riscv_controller
   output logic        load_stall_o,
   // CONFIG_REGION: NO_JUMP_ADDER
   `ifdef NO_JUMP_ADDER
-  output logic        branch_stall_o,
+  output logic        branch_calc_jump_target_o,
   `endif
 
   input  logic        id_ready_i,                 // ID stage is ready
@@ -258,7 +258,7 @@ module riscv_controller
 
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    branch_stall_o   = 1'b0;
+    branch_calc_jump_target_o   = 1'b0;
     `endif
 
 
@@ -680,8 +680,7 @@ module riscv_controller
       WAIT_BRANCH_EX:
       begin
         // there is a branch in the EX stage that is taken
-        branch_stall_o = 1'b1;
-        is_decoding_o = 1'b1;
+        branch_calc_jump_target_o = 1'b1;
         halt_if_o = 1'b1;
         if (id_ready_i)
         begin
@@ -893,7 +892,14 @@ module riscv_controller
       jr_stall_o        = 1'b1;
       deassert_we_o     = 1'b1;
     end
-    `endif // MERGE_ID_EX
+    `else 
+    if ((jump_in_dec_i == BRANCH_JALR) &&
+        ((regfile_we_wb_i == 1'b1) && (reg_d_wb_is_reg_a_i == 1'b1))
+    begin
+      jr_stall_o        = 1'b1;
+      deassert_we_o     = 1'b1;
+    end
+    `endif
     `endif // THREE_PORT_REG_FILE
   end
 
diff --git a/decoder.sv b/decoder.sv
index 61222aaf..738b1323 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -290,7 +290,7 @@ module riscv_decoder
       OPCODE_JAL: begin   // Jump and Link
         // CONFIG_REGION: NO_JUMP_ADDER
         `ifdef NO_JUMP_ADDER
-        jump_in_id            = BRANCH_JAL;
+        jump_in_id          = BRANCH_JAL;
         // Calculate jump target in EX
         alu_op_a_mux_sel_o  = OP_A_CURRPC;
         alu_op_b_mux_sel_o  = OP_B_IMM;
@@ -321,7 +321,7 @@ module riscv_decoder
       OPCODE_JALR: begin  // Jump and Link Register
         // CONFIG_REGION: NO_JUMP_ADDER
         `ifdef NO_JUMP_ADDER
-        jump_in_id            = BRANCH_JALR;
+        jump_in_id          = BRANCH_JALR;
         // Calculate jump target in EX
         alu_op_a_mux_sel_o  = OP_A_CURRPC;
         alu_op_b_mux_sel_o  = OP_B_REGA_OR_FWD;
diff --git a/id_stage.sv b/id_stage.sv
index fb727356..f61d951c 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -311,7 +311,7 @@ module riscv_id_stage
   `endif
   // CONFIG_REGION: NO_JUMP_ADDER
   `ifdef NO_JUMP_ADDER
-  logic        branch_stall;
+  logic        branch_calc_jump_target;
   `endif
   logic        jr_stall;
   logic        load_stall;
@@ -945,7 +945,7 @@ module riscv_id_stage
         OP_C_REGB_OR_FWD:  alu_operand_c = operand_b_fw_id;
         // CONFIG_REGION: NO_JUMP_ADDER
         `ifdef NO_JUMP_ADDER
-        OP_C_JT:           alu_operand_c = pc_if_i; // this is the return address
+        OP_C_RA:           alu_operand_c = pc_if_i; // this is the return address
         `else
         OP_C_JT:           alu_operand_c = jump_target;
         `endif
@@ -1109,7 +1109,7 @@ module riscv_id_stage
     `endif // ONLY_ALIGNED
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    .branch_stall_i                  ( branch_stall              ),
+    .branch_calc_jump_target_i       ( branch_calc_jump_target   ),
     `endif
     // CONFIG_REGION: MUL_SUPPORT
     `ifdef MUL_SUPPORT
@@ -1353,7 +1353,7 @@ module riscv_id_stage
     `endif // ONLY_ALIGNED
     // CONFIG_REGION: NO_JUMP_ADDER
     `ifdef NO_JUMP_ADDER
-    .branch_stall_o                 ( branch_stall           ),
+    .branch_calc_jump_target_o                 ( branch_calc_jump_target           ),
     `endif
     .jr_stall_o                     ( jr_stall               ),
     .load_stall_o                   ( load_stall             ),