diff --git a/if_stage.sv b/if_stage.sv index 93a2f077..583c52d3 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -99,18 +99,18 @@ module if_stage // Next PC Selection: pc_mux_sel_i comes from id_stage.controller always_comb begin : PC_MUX - case (pc_mux_sel_i) - `INCR_PC: begin next_pc = current_pc_if_o + 32'd4; end // PC is incremented and points the next instruction - `NO_INCR: begin next_pc = current_pc_if_o; end // PC is not incremented - `PC_FROM_REGFILE: begin next_pc = pc_from_regfile_i; end // PC is taken from the regfile - `PC_FROM_IMM: begin next_pc = branch_taken; end // PC is taken from current PC in id + the immediate displacement - `PC_EXCEPTION: begin next_pc = exc_pc; end // PC that points to the exception - `EXC_PC_REG: begin next_pc = exception_pc_reg_i; end // restore the PC when exiting from interr/ecpetions - `HWLOOP_ADDR: begin next_pc = pc_from_hwloop_i; end // PC is taken from hwloop start addr + case (pc_mux_sel_i) + `INCR_PC: begin next_pc = current_pc_if_o + 32'd4; end // PC is incremented and points the next instruction + `NO_INCR: begin next_pc = current_pc_if_o; end // PC is not incremented + `PC_FROM_REGFILE: begin next_pc = pc_from_regfile_i; end // PC is taken from the regfile + `PC_FROM_IMM: begin next_pc = branch_taken; end // PC is taken from current PC in id + the immediate displacement + `PC_EXCEPTION: begin next_pc = exc_pc; end // PC that points to the exception + `EXC_PC_REG: begin next_pc = exception_pc_reg_i; end // restore the PC when exiting from interr/ecpetions + `HWLOOP_ADDR: begin next_pc = pc_from_hwloop_i; end // PC is taken from hwloop start addr `ifdef BRANCH_PREDICTION - `PC_BRANCH_PRED: begin next_pc = correct_branch; end // take pc from branch prediction + `PC_BRANCH_PRED: begin next_pc = correct_branch; end // take pc from branch prediction `endif - default: begin next_pc = current_pc_if_o + 32'd4; end + default: begin next_pc = current_pc_if_o + 32'd4; end endcase //~case (pc_mux_sel_i) end @@ -129,33 +129,33 @@ module if_stage // NOP = addi x0, x0, 0 assign instr_rdata_int = (force_nop_i == 1'b1) ? { {25 {1'b0}}, `OPCODE_OPIMM } : instr_rdata_i; - ////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // IF PC register // - ////////////////////////////////////////////////////////////////////////////////////////////////////////////// - always_ff @(posedge clk, negedge rst_n) - begin : IF_PIPELINE - if (rst_n == 1'b0) - begin : ASSERT_RESET - current_pc_if_o <= 32'h0; - end - else - begin : DEASSERT_RESET - if ( pc_mux_boot_i == 1'b1 ) - begin - // set PC to boot address if we were just reset - current_pc_if_o <= boot_addr_i; - end - else if ( dbg_set_npc == 1'b1 ) - begin - // debug units sets NPC, PC_MUX_SEL holds this value - current_pc_if_o <= dbg_pc_from_npc; - end - else if ( stall_if_i == 1'b0 ) - begin : ENABLED_PIPE - current_pc_if_o <= next_pc; - end - end - end + ////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // IF PC register // + ////////////////////////////////////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge clk, negedge rst_n) + begin : IF_PIPELINE + if (rst_n == 1'b0) + begin : ASSERT_RESET + current_pc_if_o <= 32'h0; + end + else + begin : DEASSERT_RESET + if ( pc_mux_boot_i == 1'b1 ) + begin + // set PC to boot address if we were just reset + current_pc_if_o <= boot_addr_i; + end + else if ( dbg_set_npc == 1'b1 ) + begin + // debug units sets NPC, PC_MUX_SEL holds this value + current_pc_if_o <= dbg_pc_from_npc; + end + else if ( stall_if_i == 1'b0 ) + begin : ENABLED_PIPE + current_pc_if_o <= next_pc; + end + end + end `ifdef BRANCH_PREDICTION ////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -169,8 +169,8 @@ module if_stage end else begin : DEASSERT_RESET - if (wrong_branch_taken_i) - correct_branch <= (take_branch_i) ? branch_taken : branch_not_taken; + if (wrong_branch_taken_i) + correct_branch <= (take_branch_i) ? branch_taken : branch_not_taken; end end `endif diff --git a/include/defines.sv b/include/defines.sv index 63bd48ad..f1633073 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -159,13 +159,17 @@ `define INSTR_MULH { 7'b0000001, {10 {1'b?}}, 3'b001, {5 {1'b?}}, `OPCODE_OP } `define INSTR_MULHSU { 7'b0000001, {10 {1'b?}}, 3'b010, {5 {1'b?}}, `OPCODE_OP } `define INSTR_MULHU { 7'b0000001, {10 {1'b?}}, 3'b011, {5 {1'b?}}, `OPCODE_OP } -/* +/* not implemented `define INSTR_DIV { 7'b0000001, {10 {1'b?}}, 3'b100, {5 {1'b?}}, `OPCODE_OP } `define INSTR_DIVU { 7'b0000001, {10 {1'b?}}, 3'b101, {5 {1'b?}}, `OPCODE_OP } `define INSTR_REM { 7'b0000001, {10 {1'b?}}, 3'b110, {5 {1'b?}}, `OPCODE_OP } `define INSTR_REMU { 7'b0000001, {10 {1'b?}}, 3'b111, {5 {1'b?}}, `OPCODE_OP } */ +// Source/Destination register instruction index +`define REG_RS1 19:15 +`define REG_RS2 24:20 +`define REG_RD 11:07 ////////////////////////////////////////////////////////////////////////////// @@ -289,10 +293,6 @@ `define SR_OV 5'd11 `define SR_DSX 5'd13 -//igor addon -`define REG_A 20:16 -`define REG_B 15:11 - // forwarding operand mux `define SEL_REGFILE 2'b00 `define SEL_FW_EX 2'b01 @@ -324,7 +324,7 @@ `define IMM_SB 3'b011 `define IMM_U 3'b100 `define IMM_UJ 3'b101 - +`define IMM_C4 3'b110 // PC mux selector defines `define INCR_PC 3'b000 diff --git a/riscv_core.sv b/riscv_core.sv index 0cee0452..64087e80 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -359,7 +359,7 @@ module riscv_core .exc_pc_mux_o ( exc_pc_mux_id ), .force_nop_o ( force_nop_id ), - .pc_from_regfile_fw_o ( pc_from_regfile_id ), + .pc_from_regfile_o ( pc_from_regfile_id ), .current_pc_if_i ( current_pc_if ), .current_pc_id_i ( current_pc_id ), .pc_from_immediate_o ( pc_from_immediate_id ),