diff --git a/rtl/ibex_branch_predict.sv b/rtl/ibex_branch_predict.sv
index 988099fa..87f83836 100644
--- a/rtl/ibex_branch_predict.sv
+++ b/rtl/ibex_branch_predict.sv
@@ -88,7 +88,7 @@ module ibex_branch_predict (
     endcase
   end
 
-  `ASSERT_IF(BranchInsTypeOneHot, $onehot0({instr_j, instr_b, instr_cj, instr_cb}), fetch_valid_i);
+  `ASSERT_IF(BranchInsTypeOneHot, $onehot0({instr_j, instr_b, instr_cj, instr_cb}), fetch_valid_i)
 
   // Determine branch prediction, taken if offset is negative
   assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]);
diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv
index 3a28636d..eea1c937 100644
--- a/rtl/ibex_icache.sv
+++ b/rtl/ibex_icache.sv
@@ -827,7 +827,7 @@ module ibex_icache #(
   ///////////////////////
 
   assign instr_req  = ((SpecRequest | branch_i) & lookup_grant_ic0) |
-                      |fill_ext_req;
+                      (|fill_ext_req);
 
   assign instr_addr = |fill_ext_req ? fill_ext_req_addr :
                                       lookup_addr_ic0[ADDR_W-1:BUS_W];
diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv
index 9566df8d..ee217a8c 100644
--- a/rtl/ibex_if_stage.sv
+++ b/rtl/ibex_if_stage.sv
@@ -485,8 +485,8 @@ module ibex_if_stage #(
 
     assign instr_bp_taken_o = instr_bp_taken_q;
 
-    `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken);
-    `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn);
+    `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken)
+    `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn)
   end else begin : g_no_branch_predictor
     assign instr_bp_taken_o     = 1'b0;
     assign predict_branch_taken = 1'b0;