diff --git a/vendor/google_riscv-dv.vendor.hjson b/vendor/google_riscv-dv.vendor.hjson
index d1316f52..a079e024 100644
--- a/vendor/google_riscv-dv.vendor.hjson
+++ b/vendor/google_riscv-dv.vendor.hjson
@@ -15,4 +15,5 @@
     "sample/sample_rv32imc_test.tar.gz",
   ]
 
+  patch_dir: "patches/google_riscv-dv"
 }
diff --git a/vendor/patches/google_riscv-dv/0001-csr-test-start-addr.patch b/vendor/patches/google_riscv-dv/0001-csr-test-start-addr.patch
new file mode 100644
index 00000000..f124cd4e
--- /dev/null
+++ b/vendor/patches/google_riscv-dv/0001-csr-test-start-addr.patch
@@ -0,0 +1,12 @@
+diff --git a/scripts/gen_csr_test.py b/scripts/gen_csr_test.py
+index 9a51a1a9..76c6bd19 100644
+--- a/scripts/gen_csr_test.py
++++ b/scripts/gen_csr_test.py
+@@ -214,6 +214,7 @@ def gen_setup(test_file):
+     test_file.write(".section .text.init\n")
+     test_file.write(".globl _start\n")
+     test_file.write(".option norvc\n")
++    test_file.write(".org 0x80\n")
+     test_file.write("_start:\n")
+
+