diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
index a14c237b..e20c4b19 100644
--- a/rtl/ibex_core.sv
+++ b/rtl/ibex_core.sv
@@ -1158,7 +1158,7 @@ module ibex_core import ibex_pkg::*; #(
     assign rvfi_instr_new_wb = rvfi_instr_new_wb_q;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (~rst_ni) begin
+      if (!rst_ni) begin
         rvfi_instr_new_wb_q <= 0;
       end else begin
         rvfi_instr_new_wb_q <= instr_id_done;
diff --git a/rtl/ibex_wb_stage.sv b/rtl/ibex_wb_stage.sv
index e0e23e96..afcfb486 100644
--- a/rtl/ibex_wb_stage.sv
+++ b/rtl/ibex_wb_stage.sv
@@ -86,7 +86,7 @@ module ibex_wb_stage #(
     assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (~rst_ni) begin
+      if (!rst_ni) begin
         wb_valid_q <= 1'b0;
       end else begin
         wb_valid_q <= wb_valid_d;