From 87c4f51f2a58fb15a93492108003b5abbc12b55e Mon Sep 17 00:00:00 2001
From: Markus Wegmann <atokulus@gmail.com>
Date: Mon, 2 Jan 2017 00:30:53 +0100
Subject: [PATCH] Fix syntax in python script

---
 include/riscv_config.sv  | 28 ++++++++++++++--------------
 scripts/ri5cly-manage.py | 20 ++++++++++----------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/include/riscv_config.sv b/include/riscv_config.sv
index 950366ef..1ca84c08 100644
--- a/include/riscv_config.sv
+++ b/include/riscv_config.sv
@@ -44,42 +44,42 @@
 
 // CONFIG: MUL_SUPPORT
 // will enable RISCV32M support for multiplication, division, MAC operations. Uses a lot of multiplications
-`define MUL_SUPPORT
+//`define MUL_SUPPORT
 
 // CONFIG: VEC_SUPPORT
 // will enable RISCV32V support for vector operations.
-`define VEC_SUPPORT
+//`define VEC_SUPPORT
 
 // CONFIG: HWLP_SUPPORT
 // will enable hardware loop support.
-`define HWLP_SUPPORT
+//`define HWLP_SUPPORT
 
 // CONFIG: BIT_SUPPORT
 // will enable bit manipulation and counting support.
-`define BIT_SUPPORT
-
-// CONFIG: MATH_SPECIAL_SUPPORT
-// will enable clip, min and max operations support.
-`define MATH_SPECIAL_SUPPORT
+//`define BIT_SUPPORT
 
 // CONFIG: LSU_ADDER_SUPPORT
 // will enable an additional adder in the LSU for better timings.
-`define LSU_ADDER_SUPPORT
+//`define LSU_ADDER_SUPPORT
 
 `ifdef LSU_ADDER_SUPPORT
 
 // CONFIG: PREPOST_SUPPORT
 // will enable pre/post increment load/store support support.
-`define PREPOST_SUPPORT
+//`define PREPOST_SUPPORT
 
 `endif // LSU_ADDER_SUPPORT
 
+// CONFIG: MATH_SPECIAL_SUPPORT
+// will enable clip, min and max operations support.
+//`define MATH_SPECIAL_SUPPORT
+
 
 // Dependent definitions
 
 // CONFIG: THREE_PORT_REG_FILE
 // enables 3r2w reg file (rather than 2r1w)
-`define THREE_PORT_REG_FILE
+//`define THREE_PORT_REG_FILE
 
 
 `ifndef MUL_SUPPORT
@@ -91,15 +91,15 @@
 
 // CONFIG: SIMPLE_ALU
 // will enable simplified ALU for less gates. It does not support vectors, shuffling, nor bit operations.
-//`define SIMPLE_ALU
+`define SIMPLE_ALU
 
 // CONFIG: SMALL_IF
 // will disable large FIFO in IF stage and use a more simple one.
-//`define SMALL_IF
+`define SMALL_IF
 
 // CONFIG: RV32E
 // will reduce the register file to 16 words
-//`define RV32E
+`define RV32E
 
 `endif
 `endif
diff --git a/scripts/ri5cly-manage.py b/scripts/ri5cly-manage.py
index 70965c0a..64d1e8a0 100755
--- a/scripts/ri5cly-manage.py
+++ b/scripts/ri5cly-manage.py
@@ -126,7 +126,7 @@ def restoreConfig(new_config_path, littleRISCV_path):
 def overwriteConfig(new_config_path, littleRISCV_path, backup=True):
     print("Overwriting current config (include/riscv_config.sv) with new one ({})".format(new_config_path))
     if backup:
-        backupConfig(new_config_path, littleRISCV_path):
+        backupConfig(new_config_path, littleRISCV_path)
     shutil.copy(os.path.abspath(new_config_path), os.path.abspath(littleRISCV_path + "/include/riscv_config.sv")) # Copy new config to littleRISCV
 
 
@@ -330,16 +330,16 @@ def synthesize(littleRISCV_path):
     p.wait()
 
     # Get clock of synopsys setup configuration
-        with open(os.path.abspath(littleRISCV_path+"/../../../synopsys/scripts/setup/setup.tcl"), encoding="utf8") as f:
-            content = f.readlines()
+    with open(os.path.abspath(littleRISCV_path+"/../../../synopsys/scripts/setup/setup.tcl"), encoding="utf8") as f:
+        content = f.readlines()
 
-        clock_p = re.compile("^set\sCLOCK_SLOW\s(\d+);\.*$")
-        m = clock_p.match()
+    clock_p = re.compile("^set\sCLOCK_SLOW\s(\d+);\.*$")
+    m = clock_p.match()
 
-        if m is not None:
-            clock = str(m.group(1))
-        else:
-            clock = "undefined"
+    if m is not None:
+        clock = str(m.group(1))
+    else:
+        clock = "undefined"
 
     shutil.rmtree(os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock)), ignore_errors=True)
     shutil.copytree(os.path.abspath(littleRISCV_path + "/../../../synopsys"), os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock)))
@@ -362,7 +362,7 @@ def report_specific(config_name, littleRISCV_path):
 
     if m is not None:
         clock = m.group(1)
-    else
+    else:
         clock = "undefined"
 
     return "{}\t\t{}".format(config_name,area,clock)