diff --git a/controller.sv b/controller.sv
index 192a3759..70c627c3 100644
--- a/controller.sv
+++ b/controller.sv
@@ -147,7 +147,7 @@ module riscv_controller
   always_ff @(negedge clk)
   begin
     // print warning in case of decoding errors
-    if (illegal_insn_i) begin
+    if (is_decoding_o && illegal_insn_i) begin
       $display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i,
                riscv_id_stage.current_pc_id_i);
     end
@@ -272,6 +272,7 @@ module riscv_controller
             pc_set_o     = 1'b1;
           end
 
+          // handle exceptions
           if (exc_req_i) begin
             pc_mux_sel_o = `PC_EXCEPTION;
             pc_set_o     = 1'b1;
diff --git a/id_stage.sv b/id_stage.sv
index c52e44dd..948abcd5 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -715,9 +715,9 @@ module riscv_id_stage
     .irq_i                ( irq_i            ),
     .irq_enable_i         ( irq_enable_i     ),
 
-    .illegal_insn_i       ( illegal_insn_dec ),
-    .ecall_insn_i         ( ecall_insn_dec   ),
-    .eret_insn_i          ( eret_insn_dec    ),
+    .illegal_insn_i       ( id_valid_o & is_decoding_o & illegal_insn_dec ),
+    .ecall_insn_i         ( id_valid_o & is_decoding_o & ecall_insn_dec   ),
+    .eret_insn_i          ( id_valid_o & is_decoding_o & eret_insn_dec    ),
 
     .cause_o              ( exc_cause_o      ),
     .save_cause_o         ( save_exc_cause_o )