diff --git a/dv/uvm/core_ibex/directed_tests/custom_macros.h b/dv/uvm/core_ibex/directed_tests/custom_macros.h index 8a927636..e4c987d4 100644 --- a/dv/uvm/core_ibex/directed_tests/custom_macros.h +++ b/dv/uvm/core_ibex/directed_tests/custom_macros.h @@ -98,20 +98,51 @@ 1 : addi t0, t0, 2; \ csrw mepc, t0; -#Accesses at start, mid and end of PMP range -#define RW_ACCESSES(pmp_addr, gran) \ - la s0, pmp_addr; \ - lw s1, 0(s0); \ - sw s1, 0(s0); \ - li s1, gran / 2; \ - add s2, s0, s1; \ - lw s1, 0(s2); \ - sw s1, 0(s2); \ - li s1, gran - 4; \ - add s2, s0, s1; \ - lw s1, 0(s2); \ +#define RW_ACCESSES_IN_M_MODE(pmp_addr, gran) \ + la s0, pmp_addr; \ + lw s1, 0(s0); \ + sw s1, 0(s0); \ + li s1, gran / 2; \ + add s2, s0, s1; \ + lw s1, 0(s2); \ + sw s1, 0(s2); \ + li s1, gran - 4; \ + add s2, s0, s1; \ + lw s1, 0(s2); \ sw s1, 0(s2); +#define RW_ACCESSES_IN_U_MODE(pmp_addr, gran) \ + la s0, pmp_addr; \ + SWITCH_TO_U_MODE_LABEL(1f); \ + 1 : lw s1, 0(s0); \ + SWITCH_TO_U_MODE_LABEL(1f); \ + 1 : sw s1, 0(s0); + +#Accesses at start, mid and end of PMP range + +#ifdef U_MODE +#define RW_ACCESSES(pmp_addr, gran) RW_ACCESSES_IN_U_MODE(pmp_addr, gran) +#else +#define RW_ACCESSES(pmp_addr, gran) RW_ACCESSES_IN_M_MODE(pmp_addr, gran) +#endif + #define SET_MSECCFG(val) \ li t1, val; \ csrs CSR_MSECCFG, t1; + +#define SWITCH_TO_U_MODE_LABEL(label) \ + li t0, MSTATUS_MPP; \ + csrc mstatus, t0; \ + la t0, label; \ + csrw mepc, t0; \ + la a0, 1f; \ + mret; \ + 1: + +#define SWITCH_TO_U_MODE_REG(reg) \ + li t0, MSTATUS_MPP; \ + csrc mstatus, t0; \ + csrw mepc, reg; \ + la a0, 1f; \ + mret; \ + 1: diff --git a/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml b/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml index 599d7c6c..63cebcb2 100644 --- a/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml +++ b/dv/uvm/core_ibex/directed_tests/directed_testlist.yaml @@ -60,7 +60,7 @@ test_srcs: empty/empty.S config: riscv-tests -- test: pmp_mseccfg_test_rlb1_l0_0 +- test: pmp_mseccfg_test_rlb1_l0_0_u0 desc: > mseccfg test iterations: 1 @@ -72,7 +72,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb1_l0_1 +- test: pmp_mseccfg_test_rlb1_l0_1_u0 desc: > mseccfg test iterations: 1 @@ -84,7 +84,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb1_l1_0 +- test: pmp_mseccfg_test_rlb1_l1_0_u0 desc: > mseccfg test iterations: 1 @@ -96,7 +96,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1 -- test: pmp_mseccfg_test_rlb1_l1_1 +- test: pmp_mseccfg_test_rlb1_l1_1_u0 desc: > mseccfg test iterations: 1 @@ -108,7 +108,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1 -- test: pmp_mseccfg_test_rlb0_l0_0 +- test: pmp_mseccfg_test_rlb0_l0_0_u0 desc: > mseccfg test iterations: 1 @@ -120,7 +120,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u0 desc: > mseccfg test iterations: 1 @@ -132,7 +132,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u0 desc: > mseccfg test iterations: 1 @@ -144,7 +144,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u0 desc: > mseccfg test iterations: 1 @@ -156,7 +156,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u0 desc: > mseccfg test iterations: 1 @@ -168,7 +168,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u0 desc: > mseccfg test iterations: 1 @@ -180,7 +180,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u0 desc: > mseccfg test iterations: 1 @@ -192,7 +192,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u0 desc: > mseccfg test iterations: 1 @@ -204,7 +204,7 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u0 desc: > mseccfg test iterations: 1 @@ -216,6 +216,162 @@ -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1 +- test: pmp_mseccfg_test_rlb1_l0_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l0_1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l1_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l1_1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1 -DU_MODE + - test: access_pmp_overlap desc: > PMP access basic test diff --git a/dv/uvm/core_ibex/directed_tests/gen_testlist.py b/dv/uvm/core_ibex/directed_tests/gen_testlist.py index ab49e130..358469a1 100644 --- a/dv/uvm/core_ibex/directed_tests/gen_testlist.py +++ b/dv/uvm/core_ibex/directed_tests/gen_testlist.py @@ -80,7 +80,7 @@ def add_configs_and_handwritten_directed_tests(): test_srcs: empty/empty.S config: riscv-tests -- test: pmp_mseccfg_test_rlb1_l0_0 +- test: pmp_mseccfg_test_rlb1_l0_0_u0 desc: > mseccfg test iterations: 1 @@ -92,7 +92,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb1_l0_1 +- test: pmp_mseccfg_test_rlb1_l0_1_u0 desc: > mseccfg test iterations: 1 @@ -104,7 +104,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb1_l1_0 +- test: pmp_mseccfg_test_rlb1_l1_0_u0 desc: > mseccfg test iterations: 1 @@ -116,7 +116,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1 -- test: pmp_mseccfg_test_rlb1_l1_1 +- test: pmp_mseccfg_test_rlb1_l1_1_u0 desc: > mseccfg test iterations: 1 @@ -128,7 +128,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1 -- test: pmp_mseccfg_test_rlb0_l0_0 +- test: pmp_mseccfg_test_rlb0_l0_0_u0 desc: > mseccfg test iterations: 1 @@ -140,7 +140,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u0 desc: > mseccfg test iterations: 1 @@ -152,7 +152,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u0 desc: > mseccfg test iterations: 1 @@ -164,7 +164,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u0 desc: > mseccfg test iterations: 1 @@ -176,7 +176,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u0 desc: > mseccfg test iterations: 1 @@ -188,7 +188,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u0 desc: > mseccfg test iterations: 1 @@ -200,7 +200,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u0 desc: > mseccfg test iterations: 1 @@ -212,7 +212,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u0 desc: > mseccfg test iterations: 1 @@ -224,7 +224,7 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1 -- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1 +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u0 desc: > mseccfg test iterations: 1 @@ -236,6 +236,162 @@ def add_configs_and_handwritten_directed_tests(): -I../../../vendor/riscv-tests/isa/macros/scalar/ -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1 +- test: pmp_mseccfg_test_rlb1_l0_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l0_1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l1_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1 -DU_MODE + +- test: pmp_mseccfg_test_rlb1_l1_1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_0_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1 -DU_MODE + +- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u1 + desc: > + mseccfg test + iterations: 1 + test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S + config: riscv-tests + gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I../../../vendor/riscv-test-env/ + -I../../../vendor/riscv-test-env/p/ + -I../../../vendor/riscv-tests/isa/macros/scalar/ + -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1 -DU_MODE + - test: access_pmp_overlap desc: > PMP access basic test diff --git a/dv/uvm/core_ibex/directed_tests/pmp_mseccfg_test/pmp_mseccfg_test.S b/dv/uvm/core_ibex/directed_tests/pmp_mseccfg_test/pmp_mseccfg_test.S index f720bc85..3ee1ed39 100644 --- a/dv/uvm/core_ibex/directed_tests/pmp_mseccfg_test/pmp_mseccfg_test.S +++ b/dv/uvm/core_ibex/directed_tests/pmp_mseccfg_test/pmp_mseccfg_test.S @@ -9,6 +9,7 @@ # at start, mid and end of the PMP region. # Target of test is to achieve functional coverage for rewriting # permissions in PMP regions with RLB 0/1. +# Test accesses in both M-mode and U-mode. #include "riscv_test.h" #include "test_macros.h" @@ -33,9 +34,32 @@ SET_PMP_TOR(pmp_region_end, pmp_region_start, pmp_permissions | PMP_TOR, region_high, region_low) \ RW_ACCESSES(pmp_region_start, PMP_GRAN) +#define ACCESS_REGION(region, offset) \ + la t0, region; \ + jalr a0, offset(t0); + +#define EXEC_ACCESS_IN_M_MODE(region) \ + ACCESS_REGION(region, 0); \ + ACCESS_REGION(region, -2); + +#define EXEC_ACCESS_IN_U_MODE(region) \ + SWITCH_TO_U_MODE_LABEL(region); \ + la s0, region; \ + addi s0, s0, -2; \ + SWITCH_TO_U_MODE_REG(s0); + +#ifdef U_MODE + #define EXEC_ACCESS(region) \ + EXEC_ACCESS_IN_U_MODE(region) +#else + #define EXEC_ACCESS(region) \ + EXEC_ACCESS_IN_M_MODE(region) +#endif + #define SET_PMP_AND_ACCESS_NAPOT(pmp_permissions, region) \ SET_PMP_NAPOT(pmp_region_start, PMP_GRAN, pmp_permissions | PMP_NAPOT, region) \ - RW_ACCESSES(pmp_region_start, PMP_GRAN) + RW_ACCESSES(pmp_region_start, PMP_GRAN) \ + EXEC_ACCESS(pmp_region_start) #define SET_DIFF_PMP_CFG(pmp_region, pmp_l, pmp_l_prev) \ PREV_PMP_CFG(pmp_l_prev, pmp_region, pmp_l) \ @@ -123,6 +147,12 @@ RVTEST_CODE_BEGIN # resetting all PMP regions and mseccfg RESET_PMP + # placing 0xffffffff just before pmp_region_start so in + # order to deal with boundary instsr as uncompressed + li t0, 0xffffffff + la t1, pmp_region_start + sw t0, -4(t1) + #ifdef RLB SET_MSECCFG(MSECCFG_RLB) #endif @@ -160,7 +190,24 @@ RVTEST_CODE_BEGIN .balign 256 mtvec_handler: + csrr t0, mcause + li t1, CAUSE_FETCH_ACCESS + beq t0, t1, restore_to_pc_before_access_fault + # jump to a valid PC if illegal instruction + # which would be when PMP has execute permissions + # in pmp_region_start + li t1, CAUSE_ILLEGAL_INSTRUCTION + beq t0, t1, restore_to_pc_before_access_fault SKIP_PC + j ret_from_mhandler + +restore_to_pc_before_access_fault: + csrw mepc, a0 + +ret_from_mhandler: + # always return to m-mode + li t0, MSTATUS_MPP + csrs mstatus, t0 mret RVTEST_CODE_END @@ -169,7 +216,9 @@ RVTEST_CODE_END RVTEST_DATA_BEGIN .balign PMP_GRAN -pmp_region_start: .zero PMP_GRAN +pmp_region_start: + jr a0 + .zero (PMP_GRAN-4) pmp_region_end: TEST_DATA