diff --git a/alu.sv b/alu.sv index 819ad74e..1aebea0d 100644 --- a/alu.sv +++ b/alu.sv @@ -85,11 +85,6 @@ module alu `ALU_SUB, `ALU_ABS: begin case (vector_mode_i) - default: // VEC_MODE32 - begin - carry_in[0] = 1'b1; - end - `VEC_MODE16: begin carry_in[0] = 1'b1; @@ -100,17 +95,17 @@ module alu begin carry_in = 4'b1111; end + + default: // VEC_MODE32 + begin + carry_in[0] = 1'b1; + end endcase end default: begin case (vector_mode_i) - default: // VEC_MODE32 - begin - carry_in[0] = 1'b0; - end - `VEC_MODE16: begin carry_in[0] = 1'b0; @@ -121,6 +116,11 @@ module alu begin carry_in = 4'b0000; end + + default: // VEC_MODE32 + begin + carry_in[0] = 1'b0; + end endcase end endcase @@ -168,11 +168,6 @@ module alu always_comb begin case(vector_mode_i) - default: // VEC_MODE32 - begin - shift_amt_left[31: 0] = shift_amt[31: 0]; - end - `VEC_MODE16: begin shift_amt_left[15: 0] = shift_amt[31:16]; @@ -186,6 +181,11 @@ module alu shift_amt_left[23:16] = shift_amt[15: 8]; shift_amt_left[31:24] = shift_amt[ 7: 0]; end + + default: // VEC_MODE32 + begin + shift_amt_left[31: 0] = shift_amt[31: 0]; + end endcase end @@ -197,16 +197,6 @@ module alu always_comb begin case(vector_mode_i) - default: // VEC_MODE32 - begin - if(operator_i == `ALU_SRA) - shift_result = $unsigned( $signed(shift_op_a) >>> shift_amt_int[4:0] ); - else if(operator_i == `ALU_ROR) - shift_result = {shift_op_a, shift_op_a} >> shift_amt_int[4:0]; - else - shift_result = shift_op_a >> shift_amt_int[4:0]; - end - `VEC_MODE16: begin if(operator_i == `ALU_SRA) @@ -238,6 +228,16 @@ module alu shift_result[ 7: 0] = shift_op_a[ 7: 0] >> shift_amt_int[ 2: 0]; end end + + default: // VEC_MODE32 + begin + if(operator_i == `ALU_SRA) + shift_result = $unsigned( $signed(shift_op_a) >>> shift_amt_int[4:0] ); + else if(operator_i == `ALU_ROR) + shift_result = {shift_op_a, shift_op_a} >> shift_amt_int[4:0]; + else + shift_result = shift_op_a >> shift_amt_int[4:0]; + end endcase; // case (vec_mode_i) end @@ -294,9 +294,9 @@ module alu (operator_i == `ALU_ABS)) begin case (vector_mode_i) - default: cmp_sign_mode[3:0] = 4'b1000; `VEC_MODE16: cmp_sign_mode[3:0] = 4'b1010; `VEC_MODE8: cmp_sign_mode[3:0] = 4'b1111; + default: cmp_sign_mode[3:0] = 4'b1000; endcase end end @@ -322,8 +322,6 @@ module alu | (is_equal_vec[1] & (is_greater_vec[0]))))))}}; case(vector_mode_i) - default:; // see default assignment - `VEC_MODE16: begin is_equal[1:0] = {2{is_equal_vec[0] & is_equal_vec[1]}}; @@ -337,6 +335,8 @@ module alu is_equal[3:0] = is_equal_vec[3:0]; is_greater[3:0] = is_greater_vec[3:0]; end + + default:; // see default assignment endcase end @@ -550,7 +550,10 @@ module alu result_o = shift_left_result; end - `ALU_SRL, `ALU_SRA, `ALU_ROR: result_o = shift_result; + `ALU_SRL, `ALU_SRA, `ALU_ROR: begin + shift_left = 1'b0; + result_o = shift_result; + end // Extension Operations `ALU_EXTWZ, `ALU_EXTWS: result_o = operand_a_i; @@ -592,8 +595,6 @@ module alu `ALU_CLB: result_o = {26'h0, clb_result}; `ALU_CNT: result_o = {26'h0, cnt_result}; - `ALU_NOP: ; // Do nothing - default: ; endcase //~case(operator_i) end diff --git a/controller.sv b/controller.sv index 9fbead46..e84da3b5 100644 --- a/controller.sv +++ b/controller.sv @@ -84,7 +84,6 @@ module controller input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now // Exception Controller Signals input logic exc_pc_sel_i, // exception execution requested - input logic pc_valid_i, // is the next_pc currently valid? input logic exc_pipe_flush_i, // flush pipeline after exception handling input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB output logic illegal_insn_o, // illegal instruction encountered @@ -501,7 +500,7 @@ module controller // we unstall the if_stage if the debug unit wants to set a new // pc, so that the new value gets written into current_pc_if and is // used by the instr_core_interface - stall_if_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_if | (~pc_valid_i) | (jump_in_id_i == `BRANCH_COND); + stall_if_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_if | (jump_in_id_i == `BRANCH_COND); stall_id_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_id; stall_ex_o = instr_ack_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | dbg_stall_i; stall_wb_o = (~lsu_ready_wb_i) | dbg_stall_i; diff --git a/exc_controller.sv b/exc_controller.sv index 52614b5e..d69e9a4c 100644 --- a/exc_controller.sv +++ b/exc_controller.sv @@ -56,7 +56,6 @@ module exc_controller input logic illegal_insn_i, // Illegal instruction encountered in ID stage input logic trap_insn_i, // Trap instruction encountered in ID stage input logic drop_instruction_i, // If branch prediction went wrong - output logic pc_valid_o, // is the PC in the IF stage currently valid? input logic clear_isr_running_i, // exit ISR routine output logic exc_pipe_flush_o, // flush pipeline and go back to sleep @@ -155,7 +154,6 @@ module exc_controller exc_running_n = exc_running_p; save_pc_if_o = 1'b0; save_pc_id_o = 1'b0; - pc_valid_o = 1'b1; exc_pc_sel_o = 1'b0; exc_pc_mux_o = `EXC_PC_NO_INCR; diff --git a/id_stage.sv b/id_stage.sv index 4be7e606..7b6ea0bc 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -189,7 +189,6 @@ module id_stage // Signals running between controller and exception controller logic illegal_insn; logic trap_hit; - logic pc_valid; logic clear_isr_running; logic exc_pipe_flush; @@ -659,7 +658,6 @@ module id_stage // Exception Controller Signals .exc_pc_sel_i ( exc_pc_sel ), - .pc_valid_i ( pc_valid ), .exc_pipe_flush_i ( exc_pipe_flush ), .trap_hit_i ( trap_hit ), .illegal_insn_o ( illegal_insn ), @@ -740,7 +738,6 @@ module id_stage .illegal_insn_i ( illegal_insn ), .trap_insn_i ( trap_insn ), .drop_instruction_i ( 1'b0 ), - .pc_valid_o ( pc_valid ), .clear_isr_running_i ( clear_isr_running ), .trap_hit_o ( trap_hit ), .exc_pipe_flush_o ( exc_pipe_flush ), diff --git a/mult.sv b/mult.sv index c5c0d77e..0180e399 100644 --- a/mult.sv +++ b/mult.sv @@ -82,11 +82,6 @@ module mult always_comb begin case(vector_mode_i) - default: // VEC_MODE32, VEC_MODE216 - begin - result[31: 0] = mac_int + op_a_sel * op_b_sel; - end - `VEC_MODE16: begin result[15: 0] = mac_int[15: 0] + op_a_sel[15: 0] * op_b_sel[15: 0]; @@ -100,6 +95,11 @@ module mult result[23:16] = mac_int[23:16] + op_a_sel[23:16] * op_b_sel[23:16]; result[31:24] = mac_int[31:24] + op_a_sel[31:24] * op_b_sel[31:24]; end + + default: // VEC_MODE32, VEC_MODE216 + begin + result[31: 0] = mac_int + op_a_sel * op_b_sel; + end endcase; // case (vec_mode_i) end