diff --git a/riscv_core.sv b/riscv_core.sv index 22fd3f2e..742845c4 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -721,6 +721,7 @@ module riscv_core .clk ( clk ), .rst_n ( rst_n ), + .fetch_enable ( fetch_enable_i ), .core_id ( core_id_i ), .cluster_id ( cluster_id_i ), diff --git a/riscv_simchecker.sv b/riscv_simchecker.sv index ce7fb263..73558ed5 100644 --- a/riscv_simchecker.sv +++ b/riscv_simchecker.sv @@ -23,7 +23,7 @@ import "DPI-C" function chandle riscv_checker_init(input int boot_addr, input int core_id, input int cluster_id); -import "DPI-C" function int riscv_checker_step(input chandle cpu, input logic [31:0] pc, input logic [31:0] instr); +import "DPI-C" function int riscv_checker_step(input chandle cpu, input longint simtime, input int cycle, input logic [31:0] pc, input logic [31:0] instr); import "DPI-C" function void riscv_checker_irq(input chandle cpu, input int irq, input int irq_no); import "DPI-C" function void riscv_checker_mem_access(input chandle cpu, input int we, input logic [31:0] addr, input logic [31:0] data); import "DPI-C" function void riscv_checker_reg_access(input chandle cpu, input logic [31:0] addr, input logic [31:0] data); @@ -94,6 +94,7 @@ module riscv_simchecker class instr_trace_t; time simtime; + int cycles; logic [31:0] pc; logic [31:0] instr; logic irq; @@ -111,6 +112,8 @@ module riscv_simchecker mailbox rdata_stack = new (4); integer rdata_writes = 0; + integer cycles; + logic [15:0] instr_compressed_id; logic is_irq_if, is_irq_id; logic [ 4:0] irq_no_id, irq_no_if; @@ -180,12 +183,6 @@ module riscv_simchecker @(negedge clk); #1; - reg_write.addr = wb_reg_addr; - reg_write.value = wb_reg_wdata; - - if (wb_reg_we) - trace.regs_write.push_back(reg_write); - // pop rdata from stack when there were pending writes while(rdata_stack.num() > 0 && rdata_writes > 0) begin rdata_writes--; @@ -194,6 +191,12 @@ module riscv_simchecker end while (!wb_valid); + reg_write.addr = wb_reg_addr; + reg_write.value = wb_reg_wdata; + + if (wb_reg_we) + trace.regs_write.push_back(reg_write); + // keep care of rdata foreach(trace.mem_access[i]) begin if (trace.mem_access[i].we) begin @@ -224,11 +227,20 @@ module riscv_simchecker riscv_checker_irq(dpi_simdata, trace.irq, trace.irq_no); - if (riscv_checker_step(dpi_simdata, trace.pc, trace.instr)) - $display("%t: Mismatch between simulator and RTL detected", trace.simtime); + if (riscv_checker_step(dpi_simdata, trace.simtime, trace.cycles, trace.pc, trace.instr)) + $display("%t: Cluster %d, Core %d: Mismatch between simulator and RTL detected", trace.simtime, cluster_id, core_id); end end + // cycle counter + always_ff @(posedge clk, negedge rst_n) + begin + if (rst_n == 1'b0) + cycles = 0; + else + cycles = cycles + 1; + end + // create rdata stack initial begin @@ -246,6 +258,8 @@ module riscv_simchecker if (pc_set) begin is_irq_if <= is_interrupt; irq_no_if <= irq_no; + end else if (if_valid) begin + is_irq_if <= 1'b0; end end @@ -274,6 +288,7 @@ module riscv_simchecker trace = new (); trace.simtime = $time; + trace.cycles = cycles; trace.pc = pc; if (is_compressed) diff --git a/riscv_tracer.sv b/riscv_tracer.sv index 757a07cc..930aed2b 100644 --- a/riscv_tracer.sv +++ b/riscv_tracer.sv @@ -30,6 +30,7 @@ module riscv_tracer input logic clk, input logic rst_n, + input logic fetch_enable, input logic [4:0] core_id, input logic [4:0] cluster_id, @@ -186,7 +187,7 @@ module riscv_tracer function void printUInstr(input string mnemonic); begin regs_write.push_back({rd, 'x}); - str = $sformatf("%-16s x%0d, 0x%0h000", mnemonic, rd, imm_u_type[31:12]); + str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000}); end endfunction // printUInstr @@ -374,11 +375,13 @@ module riscv_tracer // open/close output file for writing initial begin - #1 // delay needed for valid core_id and cluster_id + wait(rst_n == 1'b1); + wait(fetch_enable == 1'b1); $sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id); $display("[TRACER] Output filename is: %s", fn); f = $fopen(fn, "w"); - $fwrite(f, "%20s\t%6s\t%10s\t%10s\t \t%s\n", "Time", "Cycles", "PC", "Instr", "Mnemonic"); + $fwrite(f, " Time Cycles PC Instr Mnemonic\n"); + end final @@ -402,7 +405,7 @@ module riscv_tracer // wait until we are going to the next stage do begin - @(posedge clk); + @(negedge clk); // replace register written back foreach(trace.regs_write[i]) @@ -437,7 +440,7 @@ module riscv_tracer // wait until we are going to the next stage do begin - @(posedge clk); + @(negedge clk); // replace register written back foreach(trace.regs_write[i]) @@ -450,7 +453,7 @@ module riscv_tracer end // log execution - always @(posedge clk) + always @(negedge clk) begin instr_trace_t trace; @@ -501,10 +504,10 @@ module riscv_tracer `INSTR_SRA: trace.printRInstr("sra"); `INSTR_OR: trace.printRInstr("or"); `INSTR_AND: trace.printRInstr("and"); - `INSTR_EXTHS: trace.printRInstr("exths"); - `INSTR_EXTHZ: trace.printRInstr("exthz"); - `INSTR_EXTBS: trace.printRInstr("extbs"); - `INSTR_EXTBZ: trace.printRInstr("extbz"); + `INSTR_EXTHS: trace.printRInstr("p.exths"); + `INSTR_EXTHZ: trace.printRInstr("p.exthz"); + `INSTR_EXTBS: trace.printRInstr("p.extbs"); + `INSTR_EXTBZ: trace.printRInstr("p.extbz"); `INSTR_PAVG: trace.printRInstr("p.avg"); `INSTR_PAVGU: trace.printRInstr("p.avgu"); `INSTR_PSLET: trace.printRInstr("p.slet");